MAX15109 Datasheet, PDF (13/19 Pages) Maxim Integrated Products – High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator

High-Efficiency, 8A, Current-Mode Synchronous
Step-Down Switching Regulator with VID Control
Make sure that the selected capacitance can accom-
modate the input ripple current given by:
I_RMS= I_O ×
V_OUT × (V_IN - V_OUT)
V_IN
If necessary, use multiple capacitors in parallel to meet
the RMS current rating requirement.
Output Capacitor Selection
Use low-ESR ceramic capacitors to minimize the voltage
ripple due to ESR. Use the following formula to estimate
the total output voltage peak-to-peak ripple:
∆V_OUT
=
V_OUT
f_SW × L

× _1-

V_OUT
V_IN



×

^R_{ESR_COUT}

+
8
×
1
f_SW ×
C_OUT



Select the output capacitors to produce an output ripple
voltage that is less than 2% of the set output voltage.
Output Voltage Transition Timing
The IC features programmable output voltage transition
timing control. The regulator tracks the voltage on the
SS pin that is set with a current-limited (10µA) VID DAC.
A small capacitor at SS can therefore be used to set the
transition timing for startup and VID transitions.
C _SS
=
I_SS x ∆t
∆V_OUT
where ISS is the soft-start current of 10FA, δVOUT is the
output-voltage transition, and δt is the transition time.
When using large COUT capacitance values, the high-
side current limit can trigger during the soft-start period.
To ensure the correct soft-start time, tSS, choose CSS
large enough to satisfy:
C _SS
>>
C _OUT
=
V_OUT ×I_SS
(I_{HSCL_MIN} - I_OUT )
×
V_FB
IHSCL_MIN is the minimum high-side switch current-limit
value.
Skip Mode Frequency and Output Ripple
In skip mode, the switching frequency (fSKIP) and output
ripple voltage (VOUT-RIPPLE) shown in Figure 3 are cal-
culated as follows:
tON is a fixed time by design (330ns, typ); the peak
inductor current reached is:
I_{SKIP−LIMIT}
=
V_IN − V_OUT
2AV
×
t _ON
tOFF1 is the time needed for the inductor current to reach
the zero-crossing (~0A):
t
OFF1
=
L
×
I_SKIP-LIMIT
V_OUT
During tON and tOFF1, the output capacitor stores a
charge equal to:
∆Q_OUT
=
L × (I_SKIP-LIMIT
-
I_LOAD)
2
×



V_IN
2
1
- V_OUT
+
1
V_OUT



During tOFF2 (= n x tCK, number of clock cycles
skipped), the output capacitor loses this charge:
t _OFF2
=
∆Q _OUT
I_LOAD
→
t _OFF2
=
L × (I_SKIP-LIMIT
-
I_LOAD
)
2
×



V_IN
2 × I_LOAD
1
- V_OUT
+
1
V_OUT


Finally, frequency in skip mode is:
f_SKIP
=
t _ON
+
1
t _OFF1
+
t _OFF2
Output ripple in skip mode is:
VREF_EXT
RSS
CSS
SS
MAX15109
Figure 2. Setting Soft-Start Time
V_OUT-RIPPLE = V_COUT-RIPPLE + V_ESR-RIPPLE =
(I_SKIP-LIMIT - I_LOAD)
C_OUT
×
t _ON
+
R_ESR,COUT
×
(I_SKIP-LIMIT
- I_LOAD)
V_OUT-RIPPLE =
 _L×
_COUT
I_SKIP-LIMIT
× (V_IN - V_OUT
)
+

R _{ESR,COUT }

×
(I_SKIP-LIMIT
-
I_LOAD)
Size COUT based on the above formula to limit output
ripple in skip mode.
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