MAX1272 Datasheet, PDF (14/20 Pages) Maxim Integrated Products – Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range

Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
CS
DIN
HI-Z
DOUT
SCLK
MSB
ACQUISITION
4 SCLKs
POWERED UP
Figure 8. Delayed Power-Down Timing
CONVERSION
12 SCLKs
LSB
POWERED DOWN
HI-Z
POWERED UP
CS
DIN
HI-Z
DOUT
SCLK
ACQUISITION
4 SCLKs
POWERED UP
POWERED DOWN
HI-Z
POWERED UP
Figure 9. Immediate Power-Down Timing
SPI and MICROWIRE Interface
When using the SPI (Figure 10a) or MICROWIRE (Figure
10b) interfaces, set CPOL = 0 and CPHA = 0 in the SPI
master. Conversion begins with a falling edge on CS.
Three consecutive 8-bit readings are necessary to
obtain the entire 12-bit result from the ADC. DOUT data
transitions on the serial clock’s falling edge. The first 8-
bit data stream contains all leading zeros. The second
8-bit data stream contains a leading zero followed by
the MSB through D5. The third 8-bit data stream con-
tains D4–D0 followed by trailing zeros.
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