MAX15039_11 Datasheet, PDF (13/19 Pages) Maxim Integrated Products – 6A, 2MHz Step-Down Regulator with Integrated Switches Open-Drain, Power-Good Output

6A, 2MHz Step-Down Regulator
with Integrated Switches
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high imped-
ance when V_FB is above 0.925 x V_REFIN and V_REFIN is
above 0.54V for at least 48 clock cycles. PWRGD pulls
low when V_FB is below 90% of V_REFIN or V_REFIN is
below 0.54V for at least 48 clock cycles. PWRGD is low
when the IC is in shutdown mode, V_DD is below the
internal UVLO threshold, or the IC is in thermal shut-
down mode.
Programming the Output Voltage
(CTL1, CTL2)
As shown in Table 1, the output voltage is pin program-
mable by the logic states of CTL1 and CTL2. CTL1 and
CTL2 are trilevel inputs: V_DD, unconnected, and GND.
An 8.06kΩ resistor must be connected between OUT
and FB when CTL1 and CTL2 are connected to GND.
The logic states of CTL1 and CTL2 should be pro-
grammed only before power-up. Once the part is
enabled, CTL1 and CTL2 should not be changed. If the
output voltage needs to be reprogrammed, cycle
power or EN and reprogram before enabling. The out-
put voltage can be programmed continuously from
0.6V to 90% of V_IN by using a resistor-divider network
from V_OUT to FB to GND as shown in Figure 3a. CTL1
and CTL2 must be connected to GND.
Shutdown Mode
Drive EN to GND to shut down the IC and reduce quies-
cent current to 10μA (typ). During shutdown, the LX is
high impedance. Drive EN high to enable the MAX15039.
Thermal Protection
Thermal-overload protection limits total power dissipation
in the device. When the junction temperature exceeds
T_J = +165°C, a thermal sensor forces the device into
shutdown, allowing the die to cool. The thermal sensor
turns the device on again after the junction temperature
cools by 20°C, causing a pulsed output during continu-
ous overload conditions. The soft-start sequence begins
after recovery from a thermal-shutdown condition.
Applications Information
IN and V_DD Decoupling
To decrease the noise effects due to the high switching
frequency and maximize the output accuracy of
the MAX15039, decouple IN with a 22μF capacitor from
IN to PGND. Also, decouple V_DD with a 2.2μF low-ESR
ceramic capacitor from V_DD to GND. Place these
capacitors as close as possible to the IC.
Table 1. CTL1 and CTL2 Output Voltage
Selection
CTL1
CTL2
V_OUT (V)
V_OUT WHEN
USING
EXTERNAL
REFIN
(V)
GND
GND
0.6* or
V_REFIN* or
0.6 < V_OUT ≤ V_REFIN < V_OUT ≤
0.9 x V_IN**
0.9 x V_IN**
V_DD
V_DD
0.7
V_REFIN x (7/6)
GND
Unconnected
0.8
GND
V_DD
1.0
V_REFIN x (4/3)
V_REFIN x (5/3)
Unconnected
GND
1.2
V_REFIN x 2
Unconnected Unconnected
1.5
V_REFIN x 2.5
Unconnected
V_DD
V_DD
GND
1.8
V_REFIN x 3
2.0
V_REFIN x (10/3)
V_DD
Unconnected
2.5
V_REFIN x (25/6)
*Install an 8.06kΩ resistor at R3 and do not install a resistor at R4.
**Install R3 and R4 following the equation in the Compensation
Design section (see Figure 3a).
LX
MAX15039
OUT
CTL1
FB
CTL2
COMP
VOLTAGE
SELECT
LX
MAX15039
OUT
R3
8kΩ
FB
CTL1
COMP
CTL2
L
V_OUT
C_OUT
R3
R2
C3
R1 ^C1
R4
C2
a) EXTERNAL RESISTIVE DIVIDER
L
V_OUT
C_OUT
R2
C3
R1 ^C1
C2
b) INTERNAL PRESET VOLTAGES
Figure 3. Type III Compensation Network
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