MAX11661_1111 Datasheet, PDF (12/28 Pages) Maxim Integrated Products – 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs

500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11662) (continued)
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 8MHz, 50% duty cycle, 500ksps, CDOUT = 10pF, TA = -40NC to +125NC,
unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
DIGITAL INPUTS (SCLK, CS)
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Digital Input High Voltage
VIH
0.75 x
VOVDD
V
Digital Input Low Voltage
VIL
0.25 x
VOVDD
V
Digital Input Hysteresis
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
VHYST
IIL
CIN
Inputs at GND or VDD
0.15 x
VOVDD
V
0.001 Q1
FA
2
pF
Output High Voltage
VOH ISOURCE = 200µA (Note 3)
0.85 x
VOVDD
V
Output Low Voltage
High-Impedance Leakage
Current
High-Impedance Output
Capacitance
POWER SUPPLY
VOL
ISINK = 200µA (Note 3)
IOL
COUT
0.15 x
VOVDD
V
Q1.0
FA
4
pF
Positive Supply Voltage
VDD
Digital I/O Supply Voltage
VOVDD
Positive Supply Current
IVDD
(Full-Power Mode)
IOVDD
Positive Supply Current
(Full-Power Mode), No Clock
IVDD
Power-Down Current
IPD
Line Rejection
TIMING CHARACTERISTICS (Note 2)
VAIN_ = VGND
VAIN_ = VGND
Leakage only
VDD = 2.2V to 3.6V, VREF = 2.2V
2.2
3.6
V
1.5
VDD
V
1.67
mA
0.1
1.5
mA
1.3
10
FA
0.17
LSB/V
Quiet Time
CS Pulse Width
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
Data Access Time After SCLK
Falling Edge (Figure 2)
SCLK Pulse Width Low
SCLK Pulse Width High
Data Hold Time From SCLK
Falling Edge
SCLK Falling Until DOUT High
Impedance
Power-Up Time
tQ
(Note 3)
t1
(Note 3)
t2
(Note 3)
t3
(Note 3)
t4
VOVDD = 2.2V to 3.6V (Note 3)
VOVDD = 1.5V to 2.2V (Note 3)
t5
Percentage of clock period
t6
Percentage of clock period
t7
Figure 3
t8
Figure 4 (Note 3)
Conversion cycle (Note 3)
4
ns
10
ns
5
ns
1
ns
15
ns
16.5
40
60
%
40
60
%
5
ns
2.5
14
ns
1
Cycle
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