MAX11661_1111 Datasheet, PDF (10/28 Pages) Maxim Integrated Products – 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs

500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11663) (continued)
(VDD = 2.2V to 3.6V. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 1)
PARAMETER
DIGITAL OUTPUT (DOUT)
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output High Voltage
VOH
ISOURCE = 200µA
0.85 x
VVDD
V
Output Low Voltage
VOL
ISINK = 200µA
0.15 x
VVDD
V
High-Impedance Leakage
Current
IOL
Q1.0
FA
High-Impedance Output
Capacitance
COUT
4
pF
POWER SUPPLY
Positive Supply Voltage
Positive Supply Current
(Full-Power Mode)
VDD
IVDD
VAIN = VGND
2.2
3.6
V
1.76
mA
Positive Supply Current
(Full-Power Mode), No Clock
IVDD
1.48
mA
Power-Down Current
IPD
Line Rejection
TIMING CHARACTERISTICS (Note 2)
Quiet Time
tQ
CS Pulse Width
t1
CS Fall to SCLK Setup
t2
CS Falling Until DOUT High-
Impedance Disabled
t3
Leakage only
VDD = 2.2V to 3.6V
(Note 3)
(Note 3)
(Note 3)
(Note 3)
1.3
10
FA
0.17
LSB/V
4
ns
10
ns
5
ns
1
ns
Data Access Time After SCLK
Falling Edge
t4
Figure 2, VDD = 2.2V to 3.6V
15
ns
SCLK Pulse Width Low
t5
Percentage of clock period (Note 3)
40
SCLK Pulse Width High
t6
Percentage of clock period (Note 3)
40
Data Hold Time From SCLK
Falling Edge
t7
Figure 3
5
60
%
60
%
ns
SCLK Falling Until DOUT High
Impedance
t8
Figure 4 (Note 3)
2.5
14
ns
Power-Up Time
Conversion cycle (Note 3)
1
Cycle
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