MRF151A Datasheet, PDF (7/8 Pages) Tyco Electronics – The RF MOSFET Line RF Power Field-Effect Transistor N-Channel Enhancement-Mode MOSFET

RF POWER MOSFET CONSIDERATIONS
MOSFET CAPACITANCES
The physical structure of a MOSFET results in capacitors
between the terminals. The metal anode gate structure de-
termines the capacitors from gate–to–drain (C_gd), and gate–
to–source (C_gs). The PN junction formed during the
fabrication of the MOSFET results in a junction capacitance
from drain–to–source (C_ds).
These capacitances are characterized as input (C_iss), out-
put (C_oss) and reverse transfer (C_rss) capacitances on data
sheets. The relationships between the inter–terminal capaci-
tances and those given on data sheets are shown below. The
C_iss can be specified in two ways:
1. Drain shorted to source and positive voltage at the gate.
2. Positive voltage of the drain in respect to source and zero
volts at the gate. In the latter case the numbers are lower.
However, neither method represents the actual operat-
ing conditions in RF applications.
C_gd
GATE
C_gs
DRAIN
C_ds
SOURCE
C_iss = C_gd = C_gs
C_oss = C_gd = C_ds
C_rss = C_gd
LINEARITY AND GAIN CHARACTERISTICS
In addition to the typical IMD and power gain data pres-
ented, Figure 6 may give the designer additional information
on the capabilities of this device. The graph represents the
small signal unity current gain frequency at a given drain cur-
rent level. This is equivalent to f_T for bipolar transistors.
Since this test is performed at a fast sweep speed, heating of
the device does not occur. Thus, in normal use, the higher
temperatures may degrade these characteristics to some ex-
tent.
DRAIN CHARACTERISTICS
One figure of merit for a FET is its static resistance in the
full–on condition. This on–resistance, V_DS(on), occurs in the
linear region of the output characteristic and is specified un-
der specific test conditions for gate–source voltage and drain
current. For MOSFETs, V_DS(on) has a positive temperature
coefficient and constitutes an important design consideration
at high temperatures, because it contributes to the power
dissipation within the device.
GATE CHARACTERISTICS
The gate of the MOSFET is a polysilicon material, and is
electrically isolated from the source by a layer of oxide. The
input resistance is very high — on the order of 10⁹ ohms —
resulting in a leakage current of a few nanoamperes.
Gate control is achieved by applying a positive voltage
slightly in excess of the gate–to–source threshold voltage,
V_GS(th).
Gate Voltage Rating — Never exceed the gate voltage
rating. Exceeding the rated V_GS can result in permanent
damage to the oxide layer in the gate region.
Gate Termination — The gate of this device is essentially
capacitor. Circuits that leave the gate open–circuited or float-
ing should be avoided. These conditions can result in turn–
on of the device due to voltage build–up on the input
capacitor due to leakage currents or pickup.
Gate Protection — This device does not have an internal
monolithic zener diode from gate–to–source. If gate protec-
tion is required, an external zener diode is recommended.
Using a resistor to keep the gate–to–source impedance
low also helps damp transients and serves another important
function. Voltage transients on the drain can be coupled to
the gate through the parasitic gate–drain capacitance. If the
gate–to–source impedance and the rate of voltage change
on the drain are both high, then the signal coupled to the gate
may be large enough to exceed the gate–threshold voltage
and turn the device on.
HANDLING CONSIDERATIONS
When shipping, the devices should be transported only in
antistatic bags or conductive foam. Upon removal from the
packaging, careful handling procedures should be adhered
to. Those handling the devices should wear grounding straps
and devices not in the antistatic packaging should be kept in
metal tote bins. MOSFETs should be handled by the case
and not by the leads, and when testing the device, all leads
should make good electrical contact before voltage is ap-
plied. As a final note, when placing the FET into the system it
is designed for, soldering should be done with a grounded
iron.
DESIGN CONSIDERATIONS
The MRF151A is an RF Power, MOS, N–channel enhance-
ment mode field–effect transistor (FET) designed for HF and
VHF power amplifier applications.
M/A-COM Application Note AN211A, FETs in Theory and
Practice, is suggested reading for those not familiar with the
construction and characteristics of FETs.
The major advantages of RF power MOSFETs include
high gain, low noise, simple bias systems, relative immunity
from thermal runaway, and the ability to withstand severely
mismatched loads without suffering damage. Power output
can be varied over a wide range with a low power dc control
signal.
DC BIAS
The MRF151A is an enhancement mode FET and, there-
fore, does not conduct when drain voltage is applied. Drain
current flows when a positive voltage is applied to the gate.
RF power FETs require forward bias for optimum perfor-
mance. The value of quiescent drain current (I_DQ) is not criti-
cal for many applications. The MRF151A was characterized at
I_DQ = 250 mA, each side, which is the suggested minimum
value of I_DQ. For special applications such as linear amplifi-
cation, I_DQ may have to be selected to optimize the critical
parameters.
The gate is a dc open circuit and draws no current. There-
fore, the gate bias circuit may be just a simple resistive divid-
er network. Some applications may require a more elaborate
bias system.
GAIN CONTROL
Power output of the MRF151A may be controlled from its
rated value down to zero (negative gain) by varying the dc
gate voltage. This feature facilitates the design of manual
gain control, AGC/ALC and modulation systems.
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