28500-DSH-002-C_15 Datasheet, PDF (81/224 Pages) M/A-COM Technology Solutions, Inc. – Multichannel Synchronous Communications Controller

Serial Interface
2. Program the ENDAD to point at the entry STARTAD+N where N is the size of the frame to be used for the poll
mechanism; N may be zero, too.
5.2
Serial Port Interface Definition in TSBUS Mode
A port operation mode is configured by programming the TPORT_TYPE and RPORT_TYPE bit fields in RSIU and
TSIU Port Configuration registers. TPORT_TYPE and RPORT_TYPE must have the same number of time slots
configured for each TSBUS port, and STB sampling edges must be programmed the same for both receive and
transmit directions. When configured to operate in TSBUS mode, the frame synchronizing signals for both receive
and transmit directions are driven by the STB signal. This leaves the RSYNC and TSYNC unused, which become
RSTUFF and TSTUFF signals, respectively. Additionally, both RxClk and TxClk signals must be synchronized so
that the sampling of STB in both directions is consistent.
5.2.1
TSBUS Frame Synchronization Flywheel
The CX28500’s TSTB signal maintains a time-base that keeps track of the active bit in the current time slot. The
mechanism is referred to as the frame synchronization flywheel. The flywheel counts the number of bits per frame
and automatically rolls over the bit count according to the programmed mode. The TSTB input marks the first bit in
the frame. A flywheel exists for both the transmit and receive directions for each port. The TSB assertion works the
first bit of time slot in the TSBUS frame. The flywheel is synchronized when CX28500 detects TSTB = 1. Once
synchronized, the flywheel maintains synchronization without further assertion of the synchronization signal.
A time slot counter within each port is reset at the beginning of each frame and tracks the current time slot being
serviced.
5.2.2
TSBUS Change Of Frame Alignment (COFA)
A COFA condition is defined as a frame synchronization event detected when it is not expected. A COFA condition
also detects if the first occurrence of frame synchronization was not present. A COFA condition can occur only if
TSTB is asserted in any time slot position that is not the first time slot of the frame. The flywheel always counts the
number of time slots allocated to a specific TSBUS port (when the port is enabled). If TSTB is asserted at any time
other than a time coincident with CX28500’s interval flywheel rollover (the first bit of TS0), COFA is reported on
both receive and transmit port directions.
When a COFA condition is detected by the serial interface, an internal COFA signal is asserted until the COFA
condition is declared off. A COFA condition is declared off when there is a complete frame without an unexpected
TSTB pulse. Thus, an internal COFA signal is asserted for at least two frame periods. During the frame period
when the internal COFA is asserted, CX28500’s serial line processor (SIU) terminates all messages that are found
to be active during the COFA condition. For each receiver and transmitter channels found to be active and
processing a message, the corresponding message descriptor’s owner bit is returned to the Host, and a Buffer
Status Descriptor is written with the COFA error encoding. The Buffer Status Descriptor is written if the INHRBSD
bit field in the RDMA Channel Configuration register is disabled (set to 1). CX28500 then proceeds to the next
message descriptor (MD) from Table 6-39, Transmit or Receive Message Descriptor Table (TMDT) or (RMDT)
Content.
Assertion of COFA condition generates a COFA interrupt encoded in the Interrupt Status Descriptor (ISD) toward
Host if this interrupt is unmasked. (See Table 6-28, RSIU Port Configuration Register and Table 6-36, TSIU Port
Configuration Register, respectively RCOFA_EN or/and TCOFA_EN bit fields.)
If a synchronization signal (TSTB) is received (low to high transition on TSTB) while the internal COFA is asserted,
an Interrupt Descriptor with the COFA interrupt encoding is generated immediately if this interrupt is not masked.
28500-DSH-002-C
Mindspeed Technologies^®
66
Mindspeed Proprietary and Confidential