28500-DSH-002-C_15 Datasheet, PDF (111/224 Pages) M/A-COM Technology Solutions, Inc. – Multichannel Synchronous Communications Controller

Memory Organization
NOTE:
For polling to work properly and efficiently, it is mandatory that the FIRST (receive time
slot)/LAST (transmit time slot) indications be configured for each channel regardless of the
operational mode (i.e., HDLC, transparent, etc.). The polling mechanism in the CX28500
uses these markings as triggering points. When configured correctly, CX28500 polls on a
channel once at the selected poll throttle rate instead of polling at every time slot allocated
to that channel, as in the case of hyperchannels. When a channel consists of only one time
slot, as in a DSO channel, its corresponding receive time slot should have the FIRST_TS bit
set. Likewise, its corresponding transmit time slot should have the LAST_TS bit set.
Table 6-26 specifies the content of each receive time slot configuration descriptor.
Table 6-26. RSIU Time Slot Configuration Descriptor
Bit
Field Name
Value
Description
31:13
12:3
2
1
0
RSVD
RCHANNEL[9:0]
RTS_ENABLE
RMASKEN_SB
RFIRST_TS
0
Reserved.
— Logical channel number assigned to the time slot.
0
Time Slot Disabled.
1
Time Slot Enabled.
0
The RMASK_SB bit field (RSLP Channel Configuration Descriptor) is ignored. All the 8 bits of
the time slot are processed.
1
Allow data mask for the specified time slot. The bits specified by RMASK_SB bit field (RSLP
Channel Configuration Descriptor) are processed.
0
This bit field indicates that the specified time slot is not the first time slot of the logical
channel.
1
This bit field indicates that the specified time slot is the first time slot of the logical channel.
If a serial port is configured to operate in channelized mode, each channel defined to operate
over the serial port must have one time slot assigned to that logical channel that is the first
time slot for that channel. In unchannelized mode, this bit must be set in the single time slot
assigned.
GENERAL NOTE:
1. The timeslot map registers have no default values and may be active after reset, so they must be configured before activating the port.
6.6.6
RSIU Time Slot Pointer Allocation Register
There is one RSIU Time Slot Pointer Allocation Descriptor for each of CX28500’s 32 serial ports. This register sets
the start and end time slot address for the specific configured port. The difference between the configured end and
start address specifies the number of time slots allocated for the specified serial port.
6.6.6.1
Time Slot Allocation Rules
1. If both pointers point to the same location, this port should be configured to operate in unchannelized mode.
This is done by setting the RPORT_TYPE field in RSIU Port Configuration register to 0.
2. If there are two, three, or four time slots, the RPORT_TYPE field in RSIU Port Configuration register must be
set to 2, 3, or 4 respectively.
3. If there are more than four time slots, the RPORT_TYPE field in TSIU Port Configuration register must be set to
either 5, if it is not T1 framing, or 1 if it is.
28500-DSH-002-C
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