28500-DSH-002-C_15 Datasheet, PDF (184/224 Pages) M/A-COM Technology Solutions, Inc. – Multichannel Synchronous Communications Controller

CX28500 PCI Bus Latency and Utilization Analysis
A.5
Receive Messages
When dealing with received messages, the full set of PCI transactions processed by the DMA controller, per
channel, is as follows:
• Read BD: CX28500 performs a burst read of 2 dwords from Host memory. This transaction takes (3 + 2 + r)
cycles during 32-bit mode, or (3 + 1 + r) cycles during 64-bit mode.
• Data Transfer: Frame information is written to Host memory until either the end of the memory buffer, the end of
the message, or the PCI bus is lost. In the general case, this transaction takes (2 + X + w) cycles for 32-bit
mode or (2 + [(X/2)] + w) cycles for 64-bit mode. Where X is the number of dwords transferred. The longest
possible value of this interval is the remaining length of the PCI latency timer or MaxData cycles. Hence, the
transaction may take (2 + MaxData + w).
• Write Buffer Status: This transaction takes (2 + 1 + w) cycles regardless of the
32- or 64-bit PCI mode, if the ECCMODE bit of the Global Configuration Register is clear (i.e., 0). When
ECCMODE is set to 1, this transaction takes (2 + 2 + w) cycles in 32-bit PCI mode, and (2 + 1 + w) cycles in
64-bit PCI mode. This chapter was written with the former in mind (i.e., this transaction is always calculated as
(2 + 1 + w) cycles, as this is the prevalent usage mode of the device).
A.6
Transmit Messages
Considering the transmit data path, the full set of PCI transactions processed by the DMA controller, per channel, is
as follows:
• Read BD: CX28500 performs a burst read of 2 dwords from Host memory. This transaction takes (3 + 2 + r)
cycles during 32-bit mode, or (3 + 1 + r) cycles during 64-bit mode.
• Data Transfer: Frame information is read from Host memory to CX28500 until either the end of the memory
buffer, the end of the message, or the PCI bus is lost. In the general case, this transaction takes (3 + X + r)
cycles for 32-bit mode or (3 + [(X/2)] + r) cycles for 64-bit mode. Where X is the number of dwords transferred.
The largest value is the remaining length of the PCI latency timer or MaxData cycles. Hence, the transaction
may take (3 + MaxData + r).
• Write Buffer Status: This transaction takes (2 + 1 + w) cycles regardless of the 32- or 64-bit PCI mode.
A.7
Allocation of Internal SLP Buffer (FIFO) Space
The total internal buffer space for SLP usage is 32 KB in each direction—total of 64 KB full-duplex. In general, this
memory should be allocated in ratio to the channels' bit rate. For example, one logical channel (unchannelized)
working at 52 Mbps should be allocated a buffer approximately five times the size of one logical channel working at
10 Mbps.
A.8
Maximum Feasible PCI Latency
The Maximum Feasible PCI Latency for a given receive channel (max L_pci-rx) is defined as the maximum length of
time in seconds that a receive channel must wait before the first data transaction is performed from its internal SLP
buffer. This can be considered as the amount of time required to service all the transmit channels plus the amount
of time required to service all but one of the receive channels. This involves updating status and reading new buffer
descriptors for all channels in both directions, transferring data from the Host memory for all transmit channels, and
transferring data to the Host memory from the SLP internal buffer for all but one of the receive channels.
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