28500-DSH-002-C_15 Datasheet, PDF (173/224 Pages) M/A-COM Technology Solutions, Inc. – Multichannel Synchronous Communications Controller

Electrical and Mechanical Specification
Figure 10-8. EBUS Write/Read Cycle, Motorola-Style
See Notes
1
ECLK
BR*
BG*
BGACK *
EAD[31:0]
EBE[3:0]*
AS*
R/WR* (read)
R/WR* (write)
2
34
5
6 7 8 9 10
Address⁽¹¹⁾
Data
Byte Enables from EBUS Configuration Descriptor
DS*
ALAPSE = 0 ELAPSE = 0
BLAPSE = 0
GENERAL NOTE:
1. BG* assertion depends on the external bus arbiter. While BG* and BR* are both deasserted, MUSYCC
places shared EBUS signals in high impedance (three-state, shown as dashed lines).
2. One ECLK cycle after BG* assertion, MUSYCC outputs valid command bus signals: EBE, AS*, R/WR*,
and DS*.
3. Two ECLK cycles after BG* assertion, MUSYCC outputs valid EAD address signals. BGACK* assertion
occurs three ECLK cycles after BG* and BR* are both asserted.
4. ALAPSE inserts a variable number of ECLK cycles to extend AS* high pulse width and EAD address interval.
5. EAD address remains valid for one ECLK cycle after AS* falling edge. During a write transaction, MUSYCC
asserts R/WR* and outputs valid EAD write data one ECLK prior to DS* assertion. During a read transaction,
EAD data lines are inputs.
6. ELAPSE inserts a variable number of ECLK cycles to extend DS* low pulse width and EAD data interval.
Read data inputs are sampled on ECLK rising edge coincident with DS* deassertion.
7. EAD write data, EBE, R/WR*, and AS* signals remain valid for one ECLK cycle after BGACK* and DS* are
deasserted.
8. One ECLK after BGACK* deassertion, the BR* output is deasserted and the bus is parked (command bus
deasserted, EAD three-state). The bus parked state ends when the external bus arbiter deasserts BG*.
9. Command bus is unparked (three-stated) one ECLK after BG* deassertion; two different unpark phases
are shown, indicating the dependence on BG* deassertion. If BG* remained asserted until the next bus
request, then command bus remains parked until one ECLK cycle following the next BR* assertion.
Caution: Whenever BG* is deasserted, all shared EBUS signals are forced to three-state after one ECLK
cycle, regardless of whether the EBUS transaction was completed. MUSYCC does not reissue or repeat
such an aborted transaction.
10. BLAPSE inserts a variable number of ECLK cycles to extend BR* deassertion interval until the next bus
request.
11. The address line A31 must be asserted in all transactions.
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28500-DSH-002-C
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