28560-DSH-001-B Datasheet, PDF (67/274 Pages) M/A-COM Technology Solutions, Inc. – HDLC Controller

CX28560 Data Sheet
Expansion Bus (EBUS)
3.1.2
3.1.3
3.1.4
The Shared Memory Pointer (Buffer Address) is a dword–aligned address of the first
buffer to or from which data needs to be transferred from or to the EBUS. The EBUS
Base Address Offset is the address for the first EBUS transaction. In the Access
Control Field, the LENGTH bit field contains the information of the number of bytes
transferred over the PCI. The maximum PCI burst read or write of EBUS transactions
is 32 dwords.
When an EBUS_RD is issued, the CX28560 executes a PCI-bursted write of EBUS
transactions and will store the data (EAD[31:0]) in an internal buffer.
When the EBUS transaction ends, the CX28560 bursts the data over the PCI to the
location specified by Shared Memory Pointer (Buffer Address). The EBE[3:0]*
drives the programmed Byte Enabled (BE) value set in the Access Control Field
dword. If EBE[3:0]* is different from 0000, the Host must determine which bytes are
valid.
If an EBUS Write command is enabled, the CX28560 transfers—via a PCI burst
read—the data from the host memory into an internal buffer. The data is transferred
over the EBUS in a series of write transactions. The EBE[3:0]* drives the
programmed value Byte Enabled (BE) value set in the Access Control Field dword. If
EBE[3:0]* is different from 0000, the host must insert the valid bytes into the
appropriate location.
Clock
The ECLK, Expansion Bus Clock, is an inverted version of the PCI clock. The signal
is output on the ECLK signal line. Whether or not a device on the EBUS requires a
synchronous interface, the ECLK signal is available all the time the PCI clock is
available (PCLK). The EBUS clock output can be disabled by appropriately setting
the ECKEN bit field in EBUS Configuration register. If ECLK is disabled, the ECLK
output is three-stated.
After PCI reset, the ECLK output pin is three-stated and the ECKEN field in EBUS
Configuration register is cleared.
Interrupt
Similar to the CN28500, but unlike previous HDLC controllers (CN8478/CN8474/
CN8472), the CX28560 is not connected to the EINT* pin of the EBUS. The EBUS
interrupt line should be connected to PCI interrupt INTB* directly, if it is needed.
Address Duration
The CX28560 can extend the duration that the address bits are valid for any given
EBUS address phase. This is accomplished by specifying a value from 0–3 in the
ALAPSE bit field in EBUS Configuration register. The value specifies the additional
ECLK periods the address bits remain asserted. That is, a value of 0 specifies the
address remains asserted for one ECLK period, and a value of 3 specifies the address
remains asserted for four ECLK periods. Disabling the ECLK signal output does not
affect the delay mechanism.
Both pre- and post-address cycles are always present during the address phase of an
EBUS cycle. The pre-address cycle is one ECLK period long and provides the
CX28560 time to transition between the address phase and the following data phase.
The pre- and post-cycles are not included in the address duration.
28560-DSH-001-B
Mindspeed Technologies™
3-5
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