28560-DSH-001-B Datasheet, PDF (33/274 Pages) M/A-COM Technology Solutions, Inc. – HDLC Controller

CX28560 Data Sheet
Introduction
The following is a description of the block diagram.
• Host Interface (POS-PHY): This block provides the communication path of the
data between the host and the CX28560.
• PCI Host Interface: This block interfaces to the PCI bus over which the host
configures and monitors the CX28560 action.
• Expansion Bus (EBUS): The EBUS is an extension of the PCI Host Interface,
which provides host with access to control other devices on the local PC board.
• Serial Interface Unit (SIU): This block provides the interface between 32 serial
ports and the Receive and Transmit Serial Line Processors block. A temporal
buffering space is provided by the SIU that is 56 bits per port, divided as 32 bits
(4 bytes) for the transmit direction and 24 bits (3 bytes) for the receive direction.
SIU controls the data access to the Rx and Tx Serial Line Processors. Because
the CX28560 supports two types of serial ports—one is the conventional
interface, the other TSBUS interface—the SIU needs to operate depending on
serial port type (for detailed descriptor information, see Chapter 4.0).
• Transmit Serial Line Processor (TSLP): This block provides the interface
between the Buffer Controller (BUFFC) and the TSIU. Data provided by the
BUFFC is processed by the TSLP according to the channel type and passed to
the TSIU for transmission to the line.
• Receive Serial Line Processor (RSLP): This block provides the interface
between the SIU and BUFFC. The data provided by RSIU is processed by
RSLP according to the channel type before it is transferred to the BUFFC.
• BUFFC: This block provides the interface between the host and the Transmit
and Receive Serial Line Processors (TSLP and RSLP). The BUFFC contains
the main storage of data—a dual port RAM of 352 KB in the transmit direction
and 320 KB in the receive direction. This space acts as a holding buffer for
incoming (Rx) and outgoing (Tx) data.
• JTAG: This is a special test port used for serial boundary scan on a PCB, as
well as access to internal scan paths and embedded memory for test.
• Onesec: the onesec signal provides the boundaries on which the performance
monitoring counters are latched.
28560-DSH-001-B
Mindspeed Technologies™
1-15
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