28560-DSH-001-B Datasheet, PDF (56/274 Pages) M/A-COM Technology Solutions, Inc. – HDLC Controller

Host Interfaces
CX28560 Data Sheet
2.2.1.3
Register 2, Address 08h
This location contains the Class Code and Revision ID registers. The Class Code
register contains the Base Code, Sub Class, and Register Level Programming
Interface fields. These are used to specify the generic function of the CX28560. The
Revision ID register denotes the version of the device.
Table 2-4. Register 2, Address 08h
Bit Field
Name
Reset
Value
31:24 Class Code
02h
23:16 Sub Class Code 80h
15:8 Register Level
0
Programming
Interface
7:0 Revision Id
00h
Type
Description
RO Function: Network Controller
RO Type: Other
RO Indicates that there is nothing special about programming the CX28560.
RO Denotes the revision number of the CX28560. This revision Id is divided into
two 4 bit fields. Upper nibble indicates Die ID which started from 0 for this
device. The lower nibble is used for rev number, Rev A = 0, Rev B = 1, etc.
2.2.1.4
Register 3, Address 0Ch
Table 2-5. Register 3, Address 0Ch
Bit Field
Name
Reset
Value
31:24 Reserved
0
23:16 Header Type
0
15:11 Latency Timer
0
10:8 —
0
7:0 Reserved
0
Type
Description
RO Unused
RO The CX28560 is a single function device with the standard layout of
configuration register space.
RW The latency timer is an 8-bit value that specifies the maximum number of
PCI clocks that the CX28560 can keep the bus after starting the access cycle
by asserting its FRAME*. The latency timer ensures that the CX28560 has a
minimum time slot for it to own the bus, but places an upper limit on how
long it owns the bus.
RO
—
RO Unused
2-10
Mindspeed Technologies™
28560-DSH-001-B
Advance Information