28236-DSH-001-B Datasheet, PDF (61/443 Pages) M/A-COM Technology Solutions, Inc. – ATM ServiceSAR Plus with xBR Traffic Management

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Figure 2-11. CN8236 Logic Diagram (2 of 3)
2.0 Architecture Overview
2.10 Logic Diagram and Pin Descriptions
Framer Configuration I
Framer Configuration I
Control I
Transmit Cell Marker I/O
Transmit Flag I/O
Transmit Enable I/O
Receive Data I
Receive Address I/O
Receive Data Parity I
Receive Cell Marker I
Receive Flag I/O
Receive Enable I/O
Framer Control/Clock I
Transmit Clock I
AF12
AE12
AD14
AF15
AF16
AC14
AE5
AF5
AC6
AD6
AE6
AF6
AC7
AD7
AE7
AF7
AC8
AD8
AE8
AF8
AC9
AF9
AF2
AE3
AF3
AD4
AE4
AD5
AC10
AE11
AD10
AC13
AD12
FRCFG1
FRCFG0
UTOPIA1
TXSOC
TXCLAV
TXEN*
RXD15
RXD14
RXD13
RXD12
RXD11
RXD10
RXD9
RXD8
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
RXD0
RXADDR4
RXADDR3
RXADDR2
RXADDR1
RXADDR0
RXPAR
TXD15
TXD14
TXD13
ATM Physical TXD12
Interface
TXD11
TXD10
TXD9
TXD8
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
TXD0
TXADDR4
TXADDR3
TXADDR2
TXADDR1
TXADDR0
TXPAR
RXSOC
RXCLAV
RXEN*
RXCLK(FRCTRL)
TXCLK
AC16
AF17
AE17
AD17
AC17
AE18
AD18
AC18
AF19
AE19
AF20
AE20
AD20
AC20
AF21
AE21
AC21
AF22
AE22
AD22
AC22
AE16
O Transmit Data
I/O Transmit Address
O Transmit Data Parity
Processor Mode Select I
Word Select I
Word Select I
Bank Select I
Bank Select I
Write Byte-Enables I
SAR/ATM Chip Select I/O
Address Strobe I/O
Burst Last I/O
Local Processor Wait I
Write not Read I/O
Self-Test Failed I
B16 PROCMODE
B10 PADDR1
C10 PADDR0
D11 PBSEL1
A10 PBSEL0
B12 PBE3*
Local Bus
Processor
Interface
C12 PBE2*
D12 PBE1*
C11 PBE0*
A15 PCS* (PHYCS1*)
D14 PAS*
C14 PBLAST* (PHYCS2*)
A13 PWAIT*
C13 PWNR
C15 PFAIL*
PRDY*
PDAEN*
PRST*
PINT*
B13 O
B15 I/O
A16 O
D15 _OD
Memory Ready
Data/Address Enable
Reset Output
Interrupt Output
I = Input, O = Output, OD = Open Drain Output
The symbol (*) Indicates Active Low
8236_099
28236-DSH-001-B
Mindspeed Technologies™
2-27