28236-DSH-001-B Datasheet, PDF (303/443 Pages) M/A-COM Technology Solutions, Inc. – ATM ServiceSAR Plus with xBR Traffic Management

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
12.0 ATM UTOPIA Interface
12.5 UTOPIA Level 1 Mode Cell Handshake Timing
Transmit data is driven on TxData[15:0] on the rising edge of TxClk when
TxEN* is asserted. TxEN* is only asserted when there is data in the CN8236
transmit FIFO buffer. Simultaneously, the odd parity computed over the
TxData[15:0] lines is driven on to the TxPar output. The TxSOC line is driven by
the framer device to indicate start of cell. If the TxCLAV input is asserted by the
framer device, the framer device is full, and another cell is not transmitted to the
physical framer. (See Figure 12-3.)
In UTOPIA mode, the TxClk input can be connected to the CN8236 CLKD3
output; a 50% duty cycle clock derived by dividing CLK2X by three.
Figure 12-3. Transmit Timing in UTOPIA Level 1 Mode with Cell Handshake
TXCLK
TXSOC
TXCLAV
(2)
TXEN*
(1)
(3)
(4)
TXD/TXPAR
H1
*** ^{P44 P45 P46 P47 P48}
X
H1
*** ^{P48 X}
NOTE(S):
(1) _{Once transfer of a cell is started, TxClav is sampled only on the last octet of a cell.}
(2) _{TxEN* goes active if TxClav is inactive at previous rising clock edge and a complete cell in the transmit FIFO buffer.}
(3) _{TxEN* goes inactive due to TxClav being active on previous cycle.}
(4) _{TxEN* goes inactive since a complete cell is not in the transmit FIFO buffer.}
8236_072
28236-DSH-001-B
Mindspeed Technologies™
12-13