28236-DSH-001-B Datasheet, PDF (352/443 Pages) M/A-COM Technology Solutions, Inc. – ATM ServiceSAR Plus with xBR Traffic Management

14.0 CN8236 Registers
14.6 Counters and Status Registers
CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Table 14-8. 0x1e4—Local Processor Interrupt Status Register 1 (LP_ISTAT1)
Bit
Field
Size
Type
Name
Description
31
1
L
PCI_BUS_EROR
30
1
29
1
28–27
2
26
1
25
1
24
1
23–16
8
15
1
14
1
13
1
12
1
11
1
10
1
9–3
7
2
1
1
1
0
1
L
AALx_STAT
L
TX_DISCARD
—
Reserved
E
DMA_AFULL
E
FR_PAR_ERR
E
FR_SYNC_ERR
—
Reserved
E
RS_QUEUE_FULL
E
RSM_OVFL
E
RSM_HS_FULL
E
RSM_LS_FULL
E
RSM_HF_EMPT
E
RSM_LF_EMPT
—
Reserved
E
SEG_UNFL
E
SEG_HS_FULL
E
SEG_LS_FULL
This bit is set if the MERROR bit in the PCI configuration
register is set. The MERROR bit is reset by either writing a
logic 1 to the MERROR bit in the PCI configuration register,
or setting the CONFIG0(PCI_ERR_RESET) bit to a logic
high.
Whenever any bit in AALx_STAT is a logic 1, AALx_STAT is
a logic 1.
When any bit in TX_STATUS is a logic 1, TX_DISCARD is
reset to 0 after the host reads the TX_STATUS register.
Read as 0.
Set when the incoming DMA burst FIFO buffer becomes
almost full.
Set on the occurrence of a parity error on the reassembly
ATM physical interface.
Set on the occurrence of a synchronization error on the
reassembly ATM physical interface.
Read as 0.
Reassembly/segmentation queue full condition.
Reassembly overflow. Indicates that a cell was lost due to a
FIFO buffer full condition.
Set on the occurrence of a host status queue full condition.
Set on the occurrence of a local status queue full condition.
Set on the occurrence of a host free buffer queue empty
condition.
Set on the occurrence of a local free buffer queue empty
condition.
Read as 0.
Segmentation underflow indicates that a scheduled cell
could not be sent due to lack of PCI bandwidth.
Indicates that the segmentation host status queue is full.
Indicates that the segmentation local status queue is full.
14-36
Mindspeed Technologies™
28236-DSH-001-B