M02061 Datasheet, PDF (24/37 Pages) M/A-COM Technology Solutions, Inc. – 3.3 or 5 Volt Laser Driver

Functional Description
V_CC and V_CC3 status are internally monitored by the M02061 during power-up and normal operation. During
power-up the “slow-start” circuitry requires that V_CC and V_CC3 each reach an acceptable level before enabling bias
or modulation current.
Table 3-1.
Pin Connection for 3.3V and 5V V_CC
Pin Connection For:
V_CC3
SV_CC
SHDWN_OUT
C_APC
PWA
V_CC = 3.3V
Connect to V_CC
Laser Anode
V_CC = 5V
Reference for C_APC and PWA
OPEN
OPEN
External safety control switch
Capacitor between C_APC and V_CC3 or V_CC Capacitor between C_APC and V_CC3 (not V_CC)
Connect to V_CC3 or V_CC to disable
Connect to V_CC3 to disable (not V_CC)
VCC3_SEL
Connect to V_CC3 or V_CC
Connect to GND
3.3.2
Bias Current Generator and Automatic Power Control
To maintain constant average optical power, the M02061 incorporates a control loop to compensate for the
changes in laser threshold current over temperature and lifetime. The bias current will be determined by the value
of the external resistor R_APCSET and the transfer efficiency between the laser and monitor photo diode.
The photo current from the monitor photo diode mounted in the laser package is sunk at I_PIN. This photo current is
mirrored and an equivalent current is sourced from pins TxPwr_MON and APC_SET. The APC loop adjusts the laser
bias current (hence the monitor diode photo current) to maintain a voltage at APC_SET of 1 band-gap voltage or
~1.3V.
R_APCSET * I_PIN = 1.3 V
The APC loop has a time constant determined by C_APC, R_APCSET and the transfer efficiency between the laser and
monitor photo diode. The larger the C_APC capacitor the lower the bandwidth of the loop and the larger R_APCSET the
lower the loop BW.
In general, it is recommended that at least 2.2 nF of external capacitance be added externally between C_APC and
V_CC3. With use of a 2.2 nF capacitor, the bias current can reach 90% of its final value within 1ms, i.e., bias current
rise-time is less than 1ms and the APC loop bandwidth is less than 30 kHz, which should be adequate for bit rates
of 155Mbps. (and all higher bit rates).
The bias generator also includes a bias current monitor mirror (BIAS_MON), whose output current is typically 1/100th
of the bias current. This pin can be connected directly through a resistor to ground. If this function is not needed
this pin can be left open.
3.3.3
Data Inputs
Both CML and PECL inputs signals can be AC coupled to the M02061. These inputs are internally biased to
approximately V_CC3 - 1.3V. In most applications the data inputs are AC coupled with controlled impedance pcb
traces which will need to be terminated externally with a 100Ω or 150Ω resistor between the + and - inputs.
PECL and CML signals may be DC coupled to the M02061 data inputs when both the M02061 and the source of
the input signals are operating from 3.3V supplies. If the M02061 is operating from a 5V supply, PECL and CML
02061-DSH-001-G
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