28529-DSH-001-K_15 Datasheet, PDF (177/309 Pages) M/A-COM Technology Solutions, Inc. – Inverse Multiplexing for ATM (IMA) Family

Registers
2.2.20
0x17—TXIDL4 (Transmit Idle Cell Header Control Register 4)
The TXIDL4 register contains the fourth byte of the Transmit Idle Cell Header. (See 0x14—TXIDL1.)
Bit
Default
Name
7
0
TxIdl4[7]
6
0
TxIdl4[6]
5
0
TxIdl4[5]
4
0
TxIdl4[4]
3
0
TxIdl4[3]
2
0
TxIdl4[2]
1
0
TxIdl4[1]
0
1
TxIdl4[0]
Description
These bits hold the Transmit Idle Cell Header values for Octet 4 of the outgoing cell.
VCI bits
Payload-type bits
Cell Loss Priority bit
2.2.21
0x18—RXHDR1 (Receive Cell Header Control Register 1)
The RXHDR1 register contains the first byte of the Receive Cell Header. The header values direct ATM cells to the
UTOPIA port if an incoming ATM cell header matches the value in the header register. Receive Header Mask
Registers further qualify ATM cell reception. This header consists of 32 bits divided among four registers.
Bit
Default
Name
7
0
RxHdr1[7]
6
0
RxHdr1[6]
5
0
RxHdr1[5]
4
0
RxHdr1[4]
3
0
RxHdr1[3]
2
0
RxHdr1[2]
1
0
RxHdr1[1]
0
0
RxHdr1[0]
Description
These bits hold the Receive Header values for Octet 1 of the incoming cell.
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