28529-DSH-001-K_15 Datasheet, PDF (121/309 Pages) M/A-COM Technology Solutions, Inc. – Inverse Multiplexing for ATM (IMA) Family

Functional Description
At the device level, the software-controlled DevMstRst, bit 7, in the GENCTRL register (0x0F00), restarts all device
functions and sets the control and status registers, including IMA, to their default values except this bit
(DevMstRst). The DevLgcRst, bit 6, in the GENCTRL register (0x0F00) restarts all device functions in the TC block
but leaves all control registers unaffected. During a device logic reset the IMA core is held in a complete reset
state.
NOTE:
If configuring the device for pass-through operation, a minimum delay of 25 uS for
IMA_Sysclk of 66 MHz or 33 uS for IMA_Sysclk of 50 MHz is required from the release of
device reset (DevMstRst) to the first access of the IMA_RX_TRANS_TABLE register or
IMA_RX_ATM_TRANS_TABLE register (0x818/0x819).
At the port level, the PrtMstRst, bit 7, in the PMODE register (0x04), restarts all port functions and sets the
registers for the associated port to their default values except this bit (PrtMstRst). The PrtLgcRst, bit 6, in the
PMODE register (0x04) restarts all functions but leaves the port control registers unaffected.
1.15.1.2
Counters (TC Block Only)
The M2852x counters record events within the TC block. Two types of events are recorded: error events, such as
Section BIP errors, and transmission events, such as transmitted ATM cells.
Counters comprised of more than one register must be accessed by reading the least significant byte (LSB) first.
This guarantees that the value contained in each component register accurately reflects the composite counter
value at the time the LSB was read, because the counter may be updated while the component registers are being
read.
Each counter is large enough to accommodate the maximum number of events that may occur within a one-second
interval. The counters are cleared after being read. Therefore, if the counters are read every second, the
application will receive an accurate recording of all events.
1.15.1.2.1 One-second Latching
The M2852x’s implementation of one-second latching ensures the integrity of the statistics being gathered by the
network management software. Internal statistics counters can be latched at one-second intervals, which are
synchronized to the OneSecIO pin (pin AE26). Therefore, the data read from the statistic counters represents the
same one second of real-time data, independent of network management software timing.
The M2852x implements one-second latching for both status signals and counter values. When the EnStatLat (bit
5) in the GENCTRL register (0xF00) is written to a logical 1, a read from any of the status registers returns the
state of the device at the time of the previous OneSecIO (pin AE26) assertion. When the EnCntrLat (bit 4) in the
GENCTRL register (0xF00) is written to a logical 1, a read from any of the counters returns the state of the device
at the time of the previous OneSecIO (pin AE26) assertion. Every second, the counter is read, moved to the latch,
and the counter is cleared. The latch is cleared when read.
Software can configure the OneSecIO pin as an output that equals the input from the 8kHzIn divided by 8000.
When configured as an input, status registers and counters may be latched on the rising edge of this input. See Bit
0 of the GENCTRL register (0xF00).
NOTE:
When latching is disabled and a counter is wider than one byte, the LSB should be read first
to retain the values of the other bytes for a subsequent read.
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