XP1026-BD_15 Datasheet, PDF (10/13 Pages) M/A-COM Technology Solutions, Inc. – Power Amplifier

XP1026-BD
Power Amplifier
27.0-32.0 GHz
Rev. V1
App Note [1] Biasing - It is recommended to separately
bias each amplifier stage Vd1 through Vd3 at Vd(1,2,3)
=5.5V with Id1=100mA, Id2=250mA and Id3=550mA. Sepa-
rate biasing is recommended if the amplifier is to be used in
a linear application or at high levels of saturation, where
gate rectification will alter the effective gate control voltage.
For non-critical applications it is possible to parallel all
stages and adjust the common gate voltage for a total drain
current Id(total)=900mA.
[Linear Applications] - For applications where the ampli-
fier is being used in linear operation, where best IM3 (Third-
Order Intermod) performance is required at more than 5dB below P1dB, it is also recommended to use active
gate biasing to keep the drain currents constant as the RF power and temperature vary; this gives the best per-
formance and most reproducible results. Depending on the supply voltage available and the power dissipation
constraints, the bias circuit may be a single transistor or a low power operational amplifier, with a low value re-
sistor in series with the drain supply used to sense the current. The gate voltage of the pHEMT is controlled to
maintain correct drain current compensating for changes over temperature.
[Saturated Applications] - For applications where the amplifier RF output power is saturated, the optimum
drain current will vary with RF drive and each amplifier stage is best operated at a constant gate voltage. Signifi-
cant gate currents will flow at saturation and bias circuitry must allow for drain current growth under this condi-
tion to achieve best RF output power and power added efficiency. Additionally, if the input RF power level will
vary significantly, a more negative gate voltage will result in less die heating at lower RF input drive levels where
the absence of RF cooling becomes significant. Note under this bias condition, gain will then vary with RF drive.
NOTE! - For any application it is highly recommended to bias the output amplifier stage from both sides for best
RF and thermal performance.
CAUTION! - Also, make sure to properly sequence the applied voltages to ensure negative gate bias (Vg1,2,3)
is available before applying the positive drain supply (Vd1,2,3). Additionally, it is recommended that the device
gates are protected with Silicon diodes to limit the applied voltage.
App Note [2] Bias Arrangement -
[For Individual Stage Bias] (recommended for linear/saturated applications) - Each DC pad (Vd1,2,3 and
Vg1,2,3) needs to have DC bypass capacitance (100-200 pF) as close to the device as possible. Additional DC
bypass capacitance (1 nF and 3.3 uF) is also recommended. All DC pads have been tied together on chip and
device can be biased from either side.
[For Parallel Stage Bias] (general applications) - The same as Individual Stage Bias but all the drain or gate
pad DC bypass capacitors (100-200 pF) are tied together at one point after bypass capacitance. Additional DC
bypass capacitance (1 nF and 3.3 uF) is also recommended to all DC or combination (if gate or drains are tied
together) of DC bias pads. All DC pads have been tied together on chip and can be biased from either side.
NOTE! In either arrangement, for most stable performance all unused DC pads must also be bypassed with at
least 100-200 pf capacitance.
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