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LTC3789_15 Datasheet, PDF (9/30 Pages) Linear Technology – High Efficiency, Synchronous, 4-Switch Buck-Boost Controller
LTC3789
Pin Functions (SSOP/QFN)
VFB (Pin 1/Pin 26): Error Amplifier Feedback Pin. Receives
the feedback voltage for the controller from an external
resistive divider across the output.
SS (Pin 2/Pin 27): External Soft-Start Input. The LTC3789
regulates the VFB voltage to the smaller of 0.8V or the volt-
age on the SS pin. A internal 3µA pull-up current source
is connected to this pin. A capacitor to ground at this
pin sets the ramp time to final regulated output voltage.
SENSE+ (Pin 3/Pin 28): The (+) Input to the Current Sense
Comparator. The ITH pin voltage and controlled offsets
between the SENSE– and SENSE+ pins, in conjunction
with RSENSE, set the current trip threshold.
SENSE– (Pin 4/Pin 1): The (–) Input to the Current Sense
Comparator.
ITH (Pin 5/Pin 2): Error Amplifier Output and Switch-
ing Regulator Compensation Point. The channel’s
current comparator trip point increases with this control
voltage.
SGND (Pin 6/Pins 3, Exposed Pad Pin 29): Small
Signal Ground. Must be routed separately from high
current grounds to the common (–) terminals of the
CIN capacitors. In the QFN package, the exposed pad
is SGND. It must be soldered to PCB ground for rated
thermal performance.
MODE/PLLIN (Pin 7/Pin 4): Mode Selection or External
Synchronization Input to Phase Detector. This is a dual-
purpose pin. When external frequency synchronization
is not used, this pin selects the operating mode. The
pin can be tied to SGND or INTVCC. SGND or below
0.8V enables forced continuous mode. INTVCC enables
pulse-skipping mode. For external sync, apply a clock
signal to this pin. The internal PLL will synchronize the
internal oscillator to the clock, and forced continuous
mode will be enabled. The PLL composition network is
integrated into the IC.
FREQ (Pin 8/Pin 5): Frequency Set Pin. There is a precision
10µA current flowing out of this pin. A resistor to ground
sets a voltage which, in turn, programs the frequency.
Alternatively, this pin can be driven with a DC voltage to
vary the frequency of the internal oscillator.
RUN (Pin 9/Pin 6): Run Control Input. Forcing the pin
below 0.5V shuts down the controller, reducing quies-
cent current. There are 1.2µA pull-up currents for this
pin. Once the RUN pin rises above 1.22V, the IC is turned
on, and an additional 5µA pull-up current is added to
the pin.
VINSNS (Pin 10/Pin 7): VIN Sense Input to the Buck-Boost
Transition Comparator. Connect this pin to the drain of the
top N-channel MOSFET on the input side.
VOUTSNS (Pin 11/Pin 8): VOUT Sense Input to the Buck-
Boost Transition Comparator. Connect this pin to the VOUT.
ILIM (Pin 12/Pin 9): Input/Output Average Current
Sense Range Input. This pin tied to SGND, INTVCC or
left floating, sets the maximum average current sense
threshold.
IOSENSE+ (Pin 13/Pin 10): The (+) Input to the Input/Output
Average Current Sense Amplifier.
IOSENSE– (Pin 14/Pin 11): The (–) Input to the Input/Output
Average Current Sense Amplifier.
TRIM (Pin 15/Pin 12): Tie this pin to GND for normal
operation. Do not allow this pin to float.
EXTVCC (Pin 20/Pin 17): External Power Input to an
Internal LDO Connected to INTVCC. This LDO supplies
INTVCC power, bypassing the internal LDO powered from
VIN whenever EXTVCC is higher than 4.8V. See EXTVCC
Connection in the Applications Information section. Do
not exceed 14V on this pin.
For more information www.linear.com/LTC3789
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