LTC3789_15 Datasheet, PDF (17/30 Pages) Linear Technology – High Efficiency, Synchronous, 4-Switch Buck-Boost Controller

LTC3789
APPLICATIONS INFORMATION
With the typical 100Ω resistors shown here, the value of
capacitor C_F should be 1µF to 2.2µF. The current loop’s
transfer function should approximate that of the voltage
loop. Crossover frequency should be one-tenth the switch-
ing frequency, and gain should decrease by 20dB/decade.
Similar current and voltage loop transfer functions will
ensure overall system stability.
When the I_OSENSE common mode voltage is above ~3.2V,
the I_OSENSE– pin sources 10µA. The I_OSENSE+ pin, however,
sources 18.3µA, 26.6µA and 35µA when the I_LIM pin is
low, floating, and high, respectively, and when a constant
current is being regulated. The error introduced by this
mismatch can be offset to a first order by scaling the
I_OSENSE+ and I_OSENSE– resistors accordingly. For example,
if the I_OSENSE+ branch has a 100Ω resistor, the 1.83mV
across it can be replicated in the I_OSENSE– branch by using
a 182Ω resistor.
When the I_OSENSE common mode voltage falls below ~3.2V
by a diode drop, the I_OSENSE current decreases linearly; it
reaches approximately –300µA at zero volts. The values
of the diode drop and maximum current sinking can vary
by 20% to 30% due to process variation. Ensure that I_O-
SENSE ^{common mode voltage never exceeds its absolute}
maximum of 0.3V below ground. Pay special attention to
short-circuit conditions in high power applications.
Slope Compensation
Slope compensation provides stability in constant-
frequency architectures by preventing subharmonic
oscillations at high duty cycles in boost operation and at
low duty cycles in buck operation. This is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40% in the boost
region, or subtracting a ramp from the inductor current
signal at lower than 40% duty cycles in the buck region.
Normally, this results in a reduction of maximum inductor
peak current for duty cycles >40% in the boost region, or
an increase of maximum inductor current for duty cycles
<40% in the buck region. However, the LTC3789 uses a
scheme that counteracts this compensating ramp, which
allows the maximum inductor current to remain unaffected
throughout all duty cycles.
Phase-Locked Loop and Frequency Synchronization
The LTC3789 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET of the
controller to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The phase
detector is an edge sensitive digital type that provides
zero degrees phase shift between the external and internal
oscillators. This type of phase detector does not exhibit
false locking to harmonics of the external clock.
The output of the phase detector is a pair of comple-
mentary current sources that charge or discharge the
internal filter network. There is a precision 10µA of cur-
rent flowing out of the FREQ pin. This allows a single
resistor to SGND to set the switching frequency when
no external clock is applied to the MODE/PLLIN pin. The
internal switch between FREQ and the integrated PLL filter
network is on, allowing the filter network to be at the same
voltage on the FREQ pin. Operating frequency is shown
in Figure 9 and specified in the Electrical Characteristics
table. If an external clock is detected on the MODE/PLLIN
pin, the internal switch previously mentioned will turn
off and isolate the influence of the FREQ pin. Note that
the LTC3789 can only be synchronized to an external
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2
FREQ PIN VOLTAGE (V)
2.5
3789 F09
Figure 9. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
For more information www.linear.com/LTC3789
3789fc
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