LTC3789_15 Datasheet, PDF (25/30 Pages) Linear Technology – High Efficiency, Synchronous, 4-Switch Buck-Boost Controller

LTC3789
APPLICATIONS INFORMATION
• Use planes for V_IN and V_OUT to maintain good voltage
filtering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. Connect the copper areas to any
DC net (V_IN or GND). When laying out the printed circuit
board, the following checklist should be used to ensure
proper operation of the LTC3789. These items are also
illustrated in Figure 13.
• Segregate the signal and power grounds. All small-
signal components should return to the SGND pin at
one point, which is then tied to the PGND pin close to
the inductor current sense resistor R_SENSE.
• Place switch B and switch C as close to the controller as
possible, keeping the PGND, BG and SW traces short.
• Keep the high dV/dT SW1, SW2, BOOST1, BOOST2,
TG1 and TG2 nodes away from sensitive small-signal
nodes.
• The path formed by switch A, switch B, D1 and the C_IN
capacitor should have short leads and PC trace lengths.
The path formed by switch C, switch D, D2 and the
C_OUT capacitor also should have short leads and PC
trace lengths.
V_IN
QA
C_IN
SW2
SW1
L
D1
QB
QC
V_OUT
D2
QD
C_OUT
R_SENSE
LTC3789
CKT
Figure 12. Switches Layout
GND
3789 F12
• The output capacitor (–) terminals should be connected
as closely as possible to the (–) terminals of the input
capacitor.
• Connect the top driver boost capacitor C_A closely to the
BOOST1 and SW1 pins. Connect the top driver boost
capacitor C_B closely to the BOOST2 and SW2 pins.
• Connect the input capacitors C_IN and output capacitors
C_OUT closely to the power MOSFETs. These capacitors
carry the MOSFET AC current in the boost and buck
region.
• Connect V_FB pin resistive dividers to the (+) terminals of
C_OUT and signal ground. A small V_FB bypass capacitor
may be connected closely to the LTC3789 SGND pin.
The R2 connection should not be along the high current
or noise paths, such as the input capacitors.
• Route SENSE^– and SENSE⁺ leads together with mini-
mum PC trace spacing. Avoid having sense lines pass
through noisy areas, such as switch nodes. The filter
capacitor between SENSE⁺ and SENSE^– should be as
close as possible to the IC. Ensure accurate current
sensing with Kelvin connections at the sense resistor.
One layout example is shown in Figure 14.
• Connect the I_TH pin compensation network closely to
the IC, between I_TH and the signal ground pins. The
capacitor helps to filter the effects of PCB noise and
output voltage ripple voltage from the compensa-
tion loop.
• Connect the INTV_CC bypass capacitor, C_VCC, closely
to the IC, between the INTV_CC and the power ground
pins. This capacitor carries the MOSFET drivers’ current
peaks. An additional 1µF ceramic capacitor placed im-
mediately next to the INTV_CC and PGND pins can help
improve noise performance substantially.
For more information www.linear.com/LTC3789
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