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LTC3784_15 Datasheet, PDF (9/38 Pages) Linear Technology – 60V PolyPhase Synchronous Boost Controller
LTC3784
Pin Functions (QFN/SSOP)
OVMODE (Pin 12/Pin 15): Overvoltage Mode Selection
Input. This pin is used to select how the LTC3784 operates
when the output feedback voltage (VFB) is overvoltage
(>110% of its normal regulated point of 1.2V). It is also
used to determine the light-load mode of operation when
the LTC3784 is synchronized to an external clock through
the PLLIN/MODE pin.
When OVMODE is tied to ground, overvoltage protection is
enabled and the top MOSFET gates (TG1, TG2) are turned
on continuously until the overvoltage condition is cleared.
When OVMODE is grounded, the LTC3784 operates in
forced continuous mode when synchronized. There is an
internal weak pull-down resistor that pulls the OVMODE
pin to ground when it is left floating.
When OVMODE is tied to INTVCC, overvoltage protection is
disabled and TG1/TG2 are not forced on during an overvolt-
age event. Instead, the state of TG1/TG2 is determined by
the mode of operation selected by the PLLIN/MODE pin and
the inductor current. See the Operation section for more
details. When OVMODE is tied to INTVCC, the LTC3784
operates in pulse-skipping mode when synchronized.
SW2, SW1 (Pin 13, Pin 24/Pin 16, Pin 27): Switch Node.
Connect to the source of the synchronous N-channel
MOSFET, the drain of the main N-channel MOSFET and
the inductor.
TG2, TG1 (Pin 14, Pin 23/Pin 17, Pin 26): Top Gate. Con-
nect to the gate of the synchronous N-channel MOSFET.
BOOST2, BOOST1 (Pin 15, Pin 22/Pin 18, Pin 25): Float-
ing power supply for the synchronous N-channel MOSFET.
Bypass to SW with a capacitor and supply with a Schottky
diode connected to INTVCC.
PGND (Pin 19/Pin 22): Driver Power Ground. Connects
to the sources of bottom (main) N-channel MOSFETs and
the (–) terminal(s) of CIN and COUT.
BG2, BG1 (Pin 16, Pin 21/Pin 19, Pin 24): Bottom Gate.
Connect to the gate of the main N-channel MOSFET.
INTVCC (Pin 17/Pin 20): Output of Internal 5.4V LDO.
Power supply for control circuits and gate drivers. De-
couple this pin to GND with a minimum 4.7μF low ESR
ceramic capacitor.
EXTVCC (Pin 18/Pin 21): External Power Input to an internal
LDO Connected to INTVCC. This LDO supplies INTVCC power,
bypassing the internal LDO powered from VBIAS whenever
EXTVCC is higher than 4.8V. See EXTVCC Connection in the
Applications Information section. Do not float or exceed
14V on this pin. Connect to ground if not used.
VBIAS (Pin 20/Pin 23): Main Supply Pin. It is normally
tied to the input supply VIN or to the output of the boost
converter. A bypass capacitor should be tied between this
pin and the signal ground pin. The operating voltage range
on this pin is 4.5V to 60V (65V abs max).
PGOOD (Pin 25/Pin 28): Power Good Indicator. Open-drain
logic output that is pulled to ground when the output volt-
age is more than ±10 % away from the regulated output
voltage. To avoid false trips the output voltage must be
outside the range for 45μs before this output is activated.
ILIM (Pin 26/Pin 1): Current Comparator Sense Voltage
Range Input. This pin is used to set the peak current sense
voltage in the current comparator. Connect this pin to SGND,
leave floating or connect to INTVCC to set the peak current
sense voltage to 50mV, 75mV or 100mV, respectively.
GND (Exposed Pad Pin 29) UFD Package: Ground. Must
be soldered to PCB ground for rated thermal performance.
For more information www.linear.com/LTC3784
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