LTC3784_15 Datasheet, PDF (18/38 Pages) Linear Technology – 60V PolyPhase Synchronous Boost Controller

LTC3784
Applications Information
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease. Once the value of L is known, an
inductor with low DCR and low core losses should be
selected.
Power MOSFET Selection
Two external power MOSFETs must be selected for each
controller in the LTC3784: one N-channel MOSFET for the
bottom (main) switch, and one N-channel MOSFET for the
top (synchronous) switch.
The peak-to-peak gate drive levels are set by the INTV_CC
voltage. This voltage is typically 5.4V during start-up
(see EXTV_CC pin connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
Pay close attention to the BV_DSS specification for the
MOSFETs as well; many of the logic level MOSFETs are
limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance R_DS(ON), Miller capacitance C_MILLER, input
voltage and maximum output current. Miller capacitance,
C_MILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturer’s data
sheet. C_MILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result
is then multiplied by the ratio of the application applied
VDS to the gate charge curve specified VDS. When the IC
is operating in continuous mode, the duty cycles for the
top and bottom MOSFETs are given by:
Main Switch Duty Cycle = ^{VOUT − VIN}
V_OUT
Synchronous Switch Duty Cycle = ^VIN
V_OUT
If the maximum output current is I_OUT(MAX) and each chan-
nel takes one half of the total output current, the MOSFET
power dissipations in each channel at maximum output
current are given by:
P_MAIN
=
(V_OUT
− V_IN)V_OUT
V² _IN
⎛
• _⎝⎜
I_OUT(MAX)
2
⎞
⎠⎟
2
•(1+ δ)
• R_DS(ON) + k • V_OUT3
• ^IOUT(MAX)
2 • V_IN
• C_MILLER • f
P_SYNC
=
V_IN
V_OUT
⎛
• _⎝⎜
I_OUT(MAX)
2
⎞
⎠⎟
2
•(1+ δ) •R_DS(ON)
where d is the temperature dependency of R_DS(ON) (ap-
proximately 1Ω). The constant k, which accounts for
the loss caused by reverse recovery current, is inversely
proportional to the gate drive current and has an empirical
value of 1.7.
Both MOSFETs have I²R losses while the bottom N-channel
equation includes an additional term for transition losses,
which are highest at low input voltages. For high V_IN the
high current efficiency generally improves with larger
MOSFETs, while for low V_IN the transition losses rapidly
increase to the point that the use of a higher R_DS(ON) device
with lower C_MILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the bottom switch duty factor is low or dur-
ing overvoltage when the synchronous switch is on close
to 100% of the period.
The term (1+ d) is generally given for a MOSFET in the
form of a normalized R_DS(ON) vs Temperature curve, but
d = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
18
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