LTC3784_15 Datasheet, PDF (27/38 Pages) Linear Technology – 60V PolyPhase Synchronous Boost Controller

LTC3784
Applications Information
Design Example
As a design example, assume V_IN = 12V (nominal),
V_IN   =   22V (max), V_OUT = 24V, I_OUT(MAX) = 8A, V_{SENSE(MAX) }=
75mV, and f = 350kHz.
The components are designed based on single channel
operation. The inductance value is chosen first based on
a 30% ripple current assumption. Tie the PLLIN/MODE
pin to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
ΔI_L
=
V_IN
f •L
⎛
⎝⎜
1−
V_IN
V_OUT
⎞
⎠⎟
The largest ripple happens when V_IN = 1/2V_OUT = 12V,
where the average maximum inductor current for each
channel is:
I_MAX
=
⎛
⎝⎜
I_OUT(MAX)
2
⎞
⎠⎟
•
⎛
⎝⎜
V_OUT
V_IN
⎞
⎠⎟
=
8A
A 6.8μH inductor will produce a 31% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 9.25A.
The R_SENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
R_SENSE
≤
75mV
9.25A
=
0.008Ω
Choosing 1% resistors: R_A = 5k and R_B = 95.3k yields an
output voltage of 24.072V.
The power dissipation on the top side MOSFET in each chan-
nel can be easily estimated. Choosing a Vishay Si7848BDP
MOSFET results in: R_DS(ON) = 0.012Ω, C_MILLER = 150pF.
At maximum input voltage with T (estimated) = 50°C:
P_MAIN
=
(24V – 12V)
(12V)²
24V
•
(4A)²
• _[1+(0.005)(50°C – 25°C)_]• 0.008Ω
+ (1.7)(24V)^{3 4A} (150pF)(350kHz) = 0.7W
12V
C_OUT is chosen to filter the square current in the output.
The maximum output current peak is:
I_OUT(PEAK)
=
8
•
⎛⎝⎜
1+
31%
2
⎞⎠⎟
=
9.3A
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 46.5mV (assuming ESR
dominates the ripple).
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 8. Figure 9 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Put the bottom N-channel MOSFETs MBOT1 and MBOT2
and the top N-channel MOSFETs MTOP1 and MTOP2
in one compact area with C_OUT .
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C_INTVCC must return to the combined C_OUT (–) terminals.
The path formed by the bottom N-channel MOSFET
and the capacitor should have short leads and PC trace
lengths. The output capacitor (–) terminals should be
connected as close as possible to the source terminals
of the bottom MOSFETs.
3. Does the LTC3784 VFB pin’s resistive divider connect to
the (+) terminal of C_OUT? The resistive divider must be
connected between the (+) terminal of C_OUT and signal
ground and placed close to the VFB pin. The feedback
resistor connections should not be along the high cur-
rent input feeds from the input capacitor(s).
4. Are the SENSE^– and SENSE⁺ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE⁺ and SENSE^– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
For more information www.linear.com/LTC3784
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