LTC3737_15 Datasheet, PDF (9/24 Pages) Linear Technology – Dual 2-Phase, No RSENSE, DC/DC Controller with Output Tracking

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OPERATIO (Refer to Functional Diagram)
When a controller is in pulse skipping operation, an
internal offset at the current comparator input will assure
that the current comparator remains tripped even at zero
load current and the regulator will start to skip cycles, as
it must, in order to maintain regulation.
Short-Circuit Protection
When one of the outputs is shorted to ground (V_FB <
0.12V), the switching frequency of that controller is re-
duced to 1/3 of the normal operating frequency. The other
controller is unaffected and maintains normal operation.
The short-circuit threshold on V_FB2 is based on the
smaller of 0.12V and a fraction of the voltage on the
TRACK pin. This also allows V_OUT2 to start up and track
V_OUT1 more easily. Note that if V_OUT1 is truly short
circuited (V_OUT1 = V_FB1 = 0V), then the LTC3737 will try to
regulate V_OUT2 to 0V if a resistor divider on V_OUT1 is
connected to the TRACK pin.
Output Overvoltage Protection
As a further protection, the overvoltage comparator (OVP)
guards against transient overshoots, as well as other more
serious conditions, that may overvoltage the output. When
the feedback voltage on the V_FB pin has risen 13.33%
above the reference voltage of 0.6V, the external P-chan-
nel MOSFET is turned off until the overvoltage is cleared.
Frequency Selection and Phase-Locked Loop (PLLLPF
and SYNC/MODE Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to main-
tain low output ripple voltage.
The switching frequency of the LTC3737’s controllers can
be selected using the PLLLPF pin. If the SYNC/MODE pin
is not being driven by an external clock source, the PLLLPF
pin can be floated, tied to V_IN or tied to SGND to select
550kHz, 750kHz or 300kHz, respectively.
LTC3737
A phase-locked loop (PLL) is available on the LTC3737 to
synchronize the internal oscillator to an external clock
source that is connected to the SYNC/MODE pin. In this
case, a series RC should be connected between the
PLLLPF pin and SGND to serve as the PLL’s loop filter. The
LTC3737 phase detector adjusts the voltage on the PLLLPF
pin to align the turn-on of controller 1’s external P-channel
MOSFET to the rising edge of the synchronizing signal.
Thus, the turn-on of controller 2’s external P-channel
MOSFET is 180 degrees out of phase to the rising edge of
the external clock source.
The typical capture range of the LTC3737’s phase-locked
loop is from approximately 200kHz to 1MHz, with a
guarantee over all variations and temperature to be be-
tween 250kHz and 850kHz. In other words, the LTC3737’s
PLL is guaranteed to lock to an external clock source
whose frequency is between 250kHz and 850kHz.
Dropout Operation
When the input supply voltage (V_IN) decreases towards
the output voltage, the rate of change of the inductor
current while the external P-channel MOSFET is on (ON
cycle) decreases. This reduction means that the P-channel
MOSFET will remain on for more than one oscillator cycle
if the inductor current has not ramped up to the threshold
set by the EAMP on the I_TH pin. Further reduction in the
input supply voltage will eventually cause the P-channel
MOSFET to be turned on 100%; i.e., DC. The output
voltage will then be determined by the input voltage minus
the voltage drop across the P-channel MOSFET and the
inductor.
Undervoltage Lockout
To prevent operation of the P-channel MOSFET below safe
input voltage levels, an undervoltage lockout is incorpo-
rated in the LTC3737. When the input supply voltage (V_IN)
drops below 2.25V, the external P-channel MOSFET and
all internal circuitry are turned off except for the undervolt-
age block, which draws only a few microamperes.
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