LTC3124_15 Datasheet, PDF (8/28 Pages) Linear Technology – 15V, 5A 2-Phase Synchronous Step-Up DC/DC Converter with Output Disconnect

LTC3124
PIN FUNCTIONS
device. Place a low ESR ceramic bypass capacitor of at
least 10µF from V_IN to PGND. X5R and X7R dielectrics
are preferred for their superior voltage and temperature
characteristics.
VC (Pin 9): Error Amplifier Output. A frequency com-
pensation network is connected from this pin to SGND
to compensate the control loop. See Compensating the
Feedback Loop section for guidelines.
PWM/SYNC (Pin 6): Burst Mode Operation Select and
Oscillator Synchronization. Do not leave this pin floating.
• PWM/SYNC = High. Disable Burst Mode operation and
maintain low noise, constant frequency operation.
• PWM/SYNC = Low. The converter operates in Burst
Mode, independent of load current.
• PWM/SYNC = External CLK. The internal oscillator is
synchronized to the external CLK signal. Burst Mode
operation is disabled. A clock pulse width of 100ns
minimum is required to synchronize the oscillator.
An external resistor MUST BE connected between R_T
and SGND to program the oscillator slightly below the
desired synchronization frequency.
In non-synchronized applications, repeated clocking of
the PWM/SYNC pin to affect an operating mode change
is supported with these restrictions:
• Boost Mode (V_OUT > V_IN): I_OUT < 3mA: f_PWM/SYNC ≤
10Hz, I_OUT ≥ 3mA: f_PWM/SYNC ≤ 5kHz.
• Buck Mode (V_OUT < V_IN): I_OUT < 5mA: f_PWM/SYNC ≤
2.5Hz, I_OUT ≥ 5mA: f_PWM/SYNC ≤ 5kHz.
V_CC (Pin 7): V_CC Regulator Output. Connect a low ESR
filter capacitor of at least 4.7µF from this pin to SGND to
provide a regulated rail approximately equal to the lower of
V_IN and 4.25V. When V_OUT is higher than V_IN, and V_IN falls
below 3V, V_CC will regulate to the lower of approximately
V_OUT and 4.25V. A UVLO event occurs if V_CC drops below
1.5V, typical. Switching is inhibited, and a soft-start is
initiated when V_CC returns above 1.6V, typical.
RT (Pin 8): Frequency Adjust Pin. Connect to SGND
through an external resistor (R_T) to program the oscillator
frequency according to the formula:
FB (Pin 10): Feedback Input to the Error Amplifier. Con-
nect the resistor divider tap to this pin. Connect the top
of the divider to V_OUT and the bottom of the divider to
SGND. The output voltage can be adjusted from 2.5V to
15V according to the formula:
V_OUT
=
1.2V
•


1+
R1
R2 ^
SD (Pin 11): Logic Controlled Shutdown Input. Pulling this
pin above 1.6V enables normal, free-running operation.
Forcing this pin below 0.25V shuts the LTC3124 off, with
quiescent current below 1µA. Do not leave this pin floating.
SGND (Pin 12): Signal Ground. When laying out your PC
board, provide a short, direct path between SGND and the
ground referenced sides of all the appropriate components
connecting to pins RT, VC, and FB.
V_OUTA, V_OUTB (Pin 13, Pin 15): Output Voltage Senses and
the Source of the Internal Synchronous Rectifier MOSFETs.
Driver bias is derived from V_OUT. Connect the output filter
capacitor from V_OUT to PGND, close to the IC. A minimum
value of 10µF ceramic per phase is recommended. V_OUT is
disconnected from V_IN when SD is low. V_OUTA and V_OUTB
must be tied together.
NC (Pin 14): No Connect. Not connected internally. Connect
this pin to V_OUTA/V_OUTB to provide a wider V_OUT copper
plane on the printed circuit board.
CAP (Pin 16): Serves as the Low Reference for the Syn-
chronous Rectifiers Gate Drives. Connect a low ESR filter
capacitor (typically 100nF) from this pin to V_OUT to provide
an elevated ground rail, approximately 5.4V below V_OUT,
used to drive the synchronous rectifiers.
f_OSC
≅
56
R_T
f_SWITCH
=
f_OSC
2
≅
28
R_T
where f_OSC is in MHz and R_T is in kΩ.
3124f
8
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