LTC3124_15 Datasheet, PDF (19/28 Pages) Linear Technology – 15V, 5A 2-Phase Synchronous Step-Up DC/DC Converter with Output Disconnect

LTC3124
APPLICATIONS INFORMATION
– MODULATOR
+^gmp
I_L
η • V_IN
2 • V_OUT
• I_L
V_OUT
R_{ESR RL}
ERROR
AMPLIFIER
1.2V
REFERENCE
C_OUT
R_PL
VC _gma
FB
C_{PL R1}
R_C
C_F
R_O
R2
C_C
C_C: COMPENSATION CAPACITOR
R_C: COMPENSATION RESISTOR
3124 F07
C_F: HIGH FREQUENCY FILTER CAPACITOR
C_PL: PHASE LEAD CAPACITOR
R_PL: PHASE LEAD RESISTOR
g_ma: TRANSCONDUCTANCE AMPLIFIER INSIDE IC
R_O: OUTPUT RESISTANCE OF g_ma
g_mp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER
C_OUT: OUTPUT CAPACITOR
R_ESR: OUTPUT CAPACITOR ESR
R_L: OUTPUT RESISTANCE DEFINED AS V_OUT/I_LOAD(MAX)
R1, R2: FEEDBACK RESISTOR DIVIDER NETWORK
η: CONVERSION EFFICIENCY (~90% AT HIGHER CURRENTS)
Figure 7. Boost Converter Equivalent Model
Combining the two equations above yields:
G_DC
=
G_MP
•
G_POWER
≈
3.4
•
η• V_IN
V_OUT
• R_L
V/V
Converter efficiency η will vary with I_OUT and switching
frequency f_SWITCH as shown in the typical performance
characteristics curves.
Output Pole: P1 =
2
Hz
2π •R_L •C_OUT
Error Amplifier Pole:
P2
=
2π
•
R_O
1
• ₍C_C
+
C_F
)
Hz;
C_F
<
C_C
10
≈ ¹ Hz; ExtremelyClose toDC
2π •R_O •C_C
Error Amplifier Zero: Z1 =
1 _Hz
2π •R_C •C_C
ESR Zero: Z2 =
1
Hz
2π •R_ESR •C_OUT
RHP Zero: Z3 = ^{VIN2 • 2RL} Hz
2π • V_OUT2 •L
High Frequency Pole: P3 > ^fOSC Hz
3
Phase
Lead Zero: Z4
=
1
2π •(R1+R_PL ) •C_PL
Hz
Phase
Lead Pole:
P4 =
1
2π
•


R1•R2
R1+ R2
+
R_PL


•
C_PL
Hz
Error Amplifier Filter Pole:
P5
=
2π
•R_C
1
• ^{CC •CF}
C_C + C_F
Hz,
C_F
<
C_C
10
≈ ¹ Hz
2π •R_C •C_F
The current mode zero (Z3) is a right-half plane zero
which can be an issue in feedback control design, but is
manageable with proper external component selection.
Also note that the RHP zero is a minimum at minimum
input voltage and maximum output current for a given
output voltage. As a general rule, the frequency at which
the open-loop gain of the converter is reduced to unity,
known as the crossover frequency f_C , should be set to
less than one-sixth of the right-half plane zero (Z3), and
under one-eighth of the switching frequency f_SWITCH. Once
f_C is selected, the compensation component values can
be calculated using a Bode plot of the power stage or two
generally valid assumptions: P1 dominates the gain of the
power stage for frequencies lower than f_C and f_C is much
higher than P2. First calculate the power stage gain at f_C,
G_fC in V/V. Assuming the output pole P1 dominates G_fC
for this range, it is expressed by:
G _fC ≈
G_{DC V/V}
1+


Pf^C1^{}
2
3124f
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