LTC3124_15 Datasheet, PDF (14/28 Pages) Linear Technology – 15V, 5A 2-Phase Synchronous Step-Up DC/DC Converter with Output Disconnect

LTC3124
OPERATION
400
350
300
250
200
150
100
50
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
V_IN, FALLING (V)
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V_OUT = 2.5V
V_OUT = 5V
V_OUT = 7.5V
V_OUT = 12V
V_OUT = 15V
Figure 5. Burst Mode Output Current vs V_IN
regulation value is reached, then the LTC3124 transitions
into a very low quiescent current sleep state. In sleep, the
output switches are turned off and the LTC3124 consumes
only 25μA of quiescent current. When the output volt-
age droops approximately 1%, switching resumes. This
maximizes efficiency at very light loads by minimizing
switching and quiescent losses. Output voltage ripple in
Burst Mode operation is typically 1% to 2% peak-to-peak.
Additional output capacitance (22μF or greater), or the
addition of a small feedforward capacitor (10pF to 50pF)
connected between V_OUT and FB can help further reduce
the output ripple.
APPLICATIONS INFORMATION
PCB LAYOUT CONSIDERATIONS
The LTC3124 switches currents as high as 4.5A at high
frequencies. Special attention should be paid to the PCB
layout to ensure a stable, noise-free and efficient application
circuit. Figure 6 presents the LTC3124’s 4-layer PCB demo
board layout (the schematic of which may be obtained
from the Quick Start Guide) to outline some of the primary
considerations. A few key guidelines are outlined below:
1. A 4-layer board is highly recommended for the LTC3124
to ensure stable performance over the full operating
voltage and current range. A dedicated/solid ground
plane should be placed directly under the V_IN, V_OUTA,
V_OUTB, SWA, and SWB traces to provide a mirror plane
to minimize noise loops from high dI/dt and dV/dt
edges (see Figure 6, 2nd layer).
2. All circulating high current paths should be kept as
short as possible. Capacitor ground connections
should via down to the ground plane in the shortest
route possible. The bypass capacitors on V_IN should be
placed as close to the IC as possible and should have
the shortest possible paths to ground (see Figure 6,
top layer).
3. PGNDA pin, PGNDB pin, and the exposed pad are the
power ground connections for the LTC3124. Multiple
vias should connect the back pad directly to the ground
plane. In addition, maximization of the metallization
connected to the back pad will improve the thermal
environment and improve the power handling capabili-
ties of the IC.
4. The high current components and their connections
should all be placed over a complete ground plane to
minimize loop cross-sectional areas. This minimizes
EMI and reduces inductive drops.
5. Connections to all of the high current components
should be made as wide as possible to reduce the
series resistance. This will improve efficiency and
maximize the output current capability of the boost
converter.
6. To prevent large circulating currents from disrupting
the converters’ output voltage sensing, compensation,
and programmed switching frequency, the ground for
the resistor divider, compensation components, and
RT should be returned to the ground plane using a
via placed close to the IC and away from the power
connections.
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For more information www.linear.com/LTC3124