LTC3404 Datasheet, PDF (7/16 Pages) Linear Technology – 1.4MHz High Efficiency Monolithic Synchronous Step-Down Regulator

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OPERATIO
Main Control Loop
The LTC3404 uses a constant frequency, current mode
step-down architecture. Both the main (P-channel
MOSFET) and synchronous (N-channel MOSFET) switches
are internal. During normal operation, the internal top
power MOSFET is turned on each clock cycle when the
oscillator sets the RS latch, and turned off when the
current comparator, I_COMP, resets the RS latch. The peak
inductor current at which I_COMP resets the RS latch is
controlled by the voltage on the I_TH pin, which is the output
of error amplifier EA. The V_FB pin, described in the Pin
Functions section, allows EA to receive an output feedback
voltage from an external resistive divider. When the load
current increases, it causes a slight decrease in the feed-
back voltage, V_FB, relative to the 0.8V internal reference,
which in turn, causes the I_TH voltage to increase until the
average inductor current matches the new load current.
While the top MOSFET is off, the bottom MOSFET is turned
on until either the inductor current starts to reverse as
indicated by the current reversal comparator I_RCMP, or the
beginning of the next clock cycle.
Comparator OVDET guards against transient overshoots
>6.25% by turning the main switch off and keeping it off
until the fault is removed.
Burst Mode Operation
The LTC3404 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
tie the SYNC/MODE pin to V_IN or connect it to a logic high
(V_SYNC/MODE > 1.5V). To disable Burst Mode operation and
enable PWM pulse skipping mode, connect the SYNC/
MODE pin to GND. In this mode, the efficiency is lower at
light loads, but becomes comparable to Burst Mode
operation when the output load exceeds 50mA. The ad-
vantage of pulse skipping mode is lower output ripple and
less interference to audio circuitry.
When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 250mA,
even though the voltage at the I_TH pin indicates a lower
value. The voltage at the I_TH pin drops when the inductor’s
average current is greater than the load requirement. As
the I_TH voltage drops below approximately 0.55V, the
LTC3404
BURST comparator trips, causing the internal sleep line to
go high and forces off both power MOSFETs. The I_TH pin
is then disconnected from the output of the EA amplifier
and held a diode voltage (0.7V) above ground.
In sleep mode, both power MOSFETs are held off and a
majority of the internal circuitry is partially turned off,
reducing the quiescent current to 10µA. The load current
is now being supplied solely from the output capacitor.
When the output voltage drops, the I_TH pin reconnects to
the output of the EA amplifier and the top MOSFET is again
turned on and this process repeats.
Short-Circuit Protection
When the output is shorted to ground, the frequency of the
oscillator is reduced to about 200kHz, 1/7 the nominal
frequency. This frequency foldback ensures that the
inductor current has ample time to decay, thereby pre-
venting runaway. The oscillator’s frequency will progres-
sively increase to 1.4MHz (or the synchronized frequency)
when V_FB rises above 0.3V.
Frequency Synchronization
A phase-locked loop (PLL) is available on the LTC3404 to
allow the internal oscillator to be synchronized to an
external source connected to the SYNC/MODE pin. The
output of the phase detector at the PLL LPF pin operates
over a 0V to 2.4V range corresponding to 1MHz to 1.7MHz.
When locked, the PLL aligns the turn-on of the top
MOSFET to the rising edge of the synchronizing signal.
When the LTC3404 is clocked by an external source, Burst
Mode operation is disabled; the LTC3404 then operates in
PWM pulse skipping mode. In this mode, when the output
load is very low, current comparator I_COMP may remain
tripped for several cycles and force the main switch to stay
off for the same number of cycles. Increasing the output
load slightly allows constant frequency PWM operation to
resume. This mode exhibits low output ripple as well as
low audio noise and reduced RF interference while provid-
ing reasonable low current efficiency.
Frequency synchronization is inhibited when the feedback
voltage V_FB is below 0.6V. This prevents the external clock
from interfering with the frequency foldback for short-
circuit protection.
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