LTC3404 Datasheet, PDF (10/16 Pages) Linear Technology – 1.4MHz High Efficiency Monolithic Synchronous Step-Down Regulator

LTC3404
APPLICATIO S I FOR ATIO
voltage. The I_TH pin compensation components can be
optimized to provide stable high performance transient
response regardless of the output capacitor selected.
ESR is a direct function of the volume of the capacitor.
Manufacturers such as Taiyo-Yuden, AVX, Kemet, Sprague
and Sanyo should be considered for high performance
capacitors. The POSCAP solid electrolytic chip capacitor
available from Sanyo is an excellent choice for output bulk
capacitors due to its low ESR/size ratio. Once the ESR
requirement for C_OUT has been met, the RMS current
rating generally far exceeds the I_RIPPLE(P-P) requirement.
When using tantalum capacitors, it is critical that they are
surge tested for use in switching power supplies. A good
choice is the AVX TPS series of surface mount tantalum,
available in case heights ranging from 2mm to 4mm. Other
capacitor types include KEMET T510 and T495 series and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
V_OUT = 0.8V^{}1+ ^{RR21}
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 3.
0.8V ≤ V_OUT ≤ 6V
R2
V_FB
LTC3404
R1
GND
3404 F03
Figure 3. Setting the LTC3404 Output Voltage
Phase-Locked Loop and Frequency Synchronization
The LTC3404 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external frequency source. The frequency range
of the voltage-controlled oscillator is 1MHz to 1.7MHz. The
phase detector used is an edge sensitive digital type that
provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the har-
monics of the V_CO center frequency. The PLL hold-in range
∆f_H is equal to the capture range, ∆f_H = ∆f_C = 300kHz and
– 400kHz.
The output of the phase detector is a pair of complemen-
tary current sources charging or discharging the external
filter network on the PLL LPF pin. The relationship
between the voltage on the PLL LPF pin and operating
frequency is shown in Figure 4. A simplified block diagram
is shown in Figure 5.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V_{PPL LPF} (V)
3404 • F04
Figure 4. Relationship Between Oscillator
Frequency and Voltage at PLL LPF Pin
PHASE
2.4V
DETECTOR
SYNC/
MODE
DIGITAL
PHASE/
FREQUENCY
DETECTOR
R_LP
C_LP
PLL LPF
VCO
3404 F05
Figure 5. Phase-Locked Loop Block Diagram
If the external frequency (V_SYNC/MODE) is greater than
1.4MHz, the center frequency, current is sourced
continuously, pulling up the PLL LPF pin. When the
external frequency is less than 1.4MHz, current is sunk
continuously, pulling down the PLL LPF pin. If the
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