LTC3260_15 Datasheet, PDF (7/18 Pages) Linear Technology – Low Noise Dual Supply Inverting Charge Pump

LTC3260
Pin Functions (DFN/MSOP)
EN⁺ (Pin 1/ Pin 1): Logic Input. A logic “high” on the EN⁺
pin enables the positive low dropout (LDO⁺) regulator.
RT (Pin 2/Pin 2): Input Connection for Programming the
Switching Frequency. The RT pin servos to a fixed 1.2V
when the EN^– pin is driven to a logic “high”. A resistor from
RT to GND sets the charge pump switching frequency. If
the RT pin is tied to GND, the switching frequency defaults
to a fixed 500kHz.
BYP^– (Pin 3/ Pin 3): LDO^– Reference Bypass Pin. Connect
a capacitor from BYP^– to GND to reduce LDO^– output
noise. Leave floating if unused.
ADJ^– (Pin 4/ Pin 4): Feedback Input for the Negative Low
Dropout Regulator. This pin servos to a fixed voltage of
–1.2V when the control loop is complete.
LDO^– (Pin 5/ Pin 5): Negative Low Dropout (LDO^–) Linear
Regulator Output. This pin requires a low ESR (equivalent
series resistance) capacitor with at least 2µF capacitance
to ground for stability.
V_OUT (Pin 6/ Pin 6): Charge Pump Output Voltage. In
constant frequency mode (MODE = low) this pin is driven
to –V_IN. In Burst Mode operation, (MODE = high) this pin
voltage is regulated to –0.94 • V_IN using an internal burst
comparator with hysteretic control.
C^– (Pin 7/ Pin 7): Flying Capacitor Negative Connection.
C⁺ (Pin 8/ Pin 10): Flying Capacitor Positive Connection.
NC (Pins 8, 9 MSOP Only): No Connect. These pins are not
connected to the LTC3260 die. These pins should be left
floating, connected to ground or shorted to adjacent pins.
V_IN (Pin 9/ Pin 11): Input Voltage for Both Charge Pump
and Positive Low Dropout (LDO⁺) Regulator. V_IN should
be bypassed with a low impedance ceramic capacitor.
LDO⁺ (Pin 10/ Pin 12): Positive Low Dropout (LDO⁺)
Output. This pin requires a low ESR capacitor with at least
2µF capacitance to ground for stability.
EN^– (Pin 11/ Pin 13): Logic Input. A logic “high” on the
EN^– pin enables the inverting charge pump as well as the
negative LDO regulator.
MODE (Pin 12/ Pin 14): Logic Input. The MODE pin deter-
mines the charge pump operating mode. A logic “high”
on the MODE pin forces the charge pump to operate in
Burst Mode operation regulating V_OUT to approximately
–0.94 • V_IN with hysteretic control. A logic “low” on the
MODE pin forces the charge pump to operate as an open-
loop inverter with a constant switching frequency. The
switching frequency in both modes is determined by an
external resistor from the RT pin to GND. In Burst Mode
operation, this represents the frequency of the burst cycles
before the part enters the low quiescent current sleep state.
ADJ⁺ (Pin 13/ Pin 15): Feedback Input for the Positive
Low Dropout (LDO⁺) Regulator. This pin servos to a fixed
voltage of 1.2V when the control loop is complete.
BYP⁺ (Pin 14/Pin 16): LDO⁺ Reference Bypass Pin. Con-
nect a capacitor from BYP⁺ to GND to reduce LDO⁺ output
noise. Leave floating if unused.
GND (Exposed Pad Pin 15/ Exposed Pad Pin 17): Ground.
The exposed package pad is ground and must be soldered
to the PC board ground plane for proper functionality and
for rated thermal performance.
3260fa
7