LTC3260_15 Datasheet, PDF (10/18 Pages) Linear Technology – Low Noise Dual Supply Inverting Charge Pump

LTC3260
Operation (Refer to the Block Diagram)
Figure 2 shows the LDO⁺ regulator application circuit.
The LDO⁺ output voltage V_LDO+ can be programmed by
choosing suitable values of R1 and R2 such that:
V_LDO⁺
=
1.2V
•


R1
R2
+
1^{}
An optional capacitor of 10nF can be connected from the
BYP⁺ pin to ground. This capacitor bypasses the internal
1.2V reference of the LTC3260 and improves the noise
performance of the LDO⁺. If this function is not used the
BYP⁺ pin should be left floating.
LTC3260
0
EN⁺
1
1.2V
REF
V_IN
LDO⁺
ADJ⁺
BYP⁺
GND
LDO
OUTPUT
R1
C_OUT
R2
C_BYP+
3260 F02
Figure 2: Positive LDO Application Circuit
Negative Low Dropout Linear Regulator (LDO^–)
The negative low dropout regulator (LDO^–) supports a
load of up to 50mA. The LDO^– takes power from the V_OUT
pin (output of the inverting charge pump) and drives the
LDO^– output pin to a voltage programmed by the resis-
tor divider connected between the LDO^–, ADJ^– and GND
pins. For stability, the LDO^– output must be bypassed to
ground with a low ESR ceramic capacitor that maintains a
capacitance of at least 2µF across operating temperature
and voltage.
The LDO^– is enabled or disabled via the EN^– logic input
pin. Initially, when the EN^– logic input is low, the charge
pump circuitry is disabled and the V_OUT pin is at GND.
When EN^– is switched high, the V_OUT pin will be driven
negative by the charge pump circuitry. Soft-start circuitry
in the charge pump also provides soft-start functionality
for the LDO^– and prevents excessive inrush currents.
Figure 3 shows the LDO^– regulator application circuit.
The LDO^– output voltage V_LDO– can be programmed by
choosing suitable values of R1 and R2 such that:
V_LDO–
=
–1.2V
•


R1
R2
+
1^{}
When the inverting charge pump is in Burst Mode opera-
tion (MODE = high), the typical hysteresis on the V_OUT
pin is 2% of V_IN voltage. The LDO^– voltage should be set
high enough above V_OUT in order to prevent LDO^– from
entering dropout during normal operation.
An optional capacitor of 10nF can be connected from the
BYP^– pin to ground. This capacitor bypasses the internal
–1.2V reference of the LTC3260 and improves the noise
performance of the LDO^–. If this function is not used the
BYP ^– pin should be left floating.
In order to improve transient response, an optional
capacitor, C_ADJ–, may be used as shown in Figure 3. A
recommended value for C_ADJ– is 10pF. Experimentation
with capacitor values between 2pF and 22pF may yield
improved transient response.
–1.2V
REF
LTC3260
GND
BYP^–
ADJ^–
1
EN^–
0
LDO^–
V_OUT
C_BYP–
R2
C_ADJ–
R1
LDO
OUTPUT
C_OUT
3260 F03
Figure 3: Negative LDO Application Circuit
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