LTC3737 Datasheet, PDF (6/24 Pages) Linear Technology – Dual 2-Phase, No RSENSE DC/DC Controller with Output Tracking

LTC3737
PI FU CTIO S (QFN/SSOP)
I_TH1, I_TH2 (Pins 1, 8/Pins 4, 11): Current Threshold and
Error Amplifier Compensation Point. Nominal operating
range on these pins is from 0.7V to 2V. The voltage on this
pin determines the threshold of the main current
comparator.
PLLLPF (Pin 3/Pin 6): Frequency Set/PLL Lowpass Filter.
When synchronizing to an external clock, this pin serves as
the lowpass filter point for the phase-locked loop. Nor-
mally, a series RC is connected between this pin and
ground.
When not synchronizing to an external clock, this pin serves
as the frequency select input. Tying this pin to GND selects
300kHz operation; tying this pin to V_IN selects 750kHz
operation. Floating this pin selects 550kHz operation.
SGND (Pin 4/Pin 7): Signal Ground. This pin serves as the
ground connection for most internal circuits.
V_IN (Pin 5/Pin 8): Chip Signal Power Supply. This pin
powers the entire chip except for the gate drivers. Exter-
nally filtering this pin with a lowpass RC network (e.g., R
= 10Ω, C = 1µF) is suggested to minimize noise pickup,
especially in high load current applications.
TRACK (Pin 6/Pin 9): Tracking Input for Second Control-
ler. This pin allows the start-up of V_OUT2 to “track” that of
V_OUT1 according to a ratio established by a resistor divider
on V_OUT1 connected to the TRACK pin. For one-to-one
tracking of V_OUT1 and V_OUT2 during start-up, a resistor
divider with values equal to those connected to V_FB2 from
V_OUT2 should be used to connect to TRACK from V_OUT1.
PGOOD (Pin 9/Pin 12): Power Good Output Voltage Moni-
tor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (V_FB1, V_FB2) is not
within ±13.3% of its nominal set point.
NC (Pins 13, 19/Pins 16, 22): No Connect.
RUN/SS (Pin 14/Pin 17): Run Control Input and Optional
External Soft-Start Input. Forcing this pin below 0.65V
shuts down the chip (both channels). Driving this pin to
V_IN or releasing this pin enables the chip to start-up with
the internal soft-start. An external soft-start can be pro-
grammed by connecting a capacitor between this pin and
ground.
PGND (Pin 16/Pin 19): Power Ground. This pin serves as
the ground connection for the gate drivers.
PGATE1, PGATE2 (Pins 17, 15/Pins 20, 18): Gate Drives
for External P-Channel MOSFETs. These pins have an
output swing from PGND to SENSE⁺.
SYNC/MODE (Pin 18/Pin 21): External Clock Synchroni-
zation and Burst Mode/Pulse Skipping Select. Applying a
clock with frequency between 250kHz to 850kHz causes
the internal oscillator to phase lock to the external clock,
and disables Burst Mode operation but allows pulse skip-
ping at low load currents. Forcing this pin high enables
Burst Mode operation. Forcing this pin low enables pulse-
skipping mode. In these cases, the frequency of the
internal oscillator is set by the voltage on the PLLLPF pin.
Do not let this pin float.
PV_IN1, PV_IN2 (Pins 20, 12/Pins 23, 15): Powers of the
Gate Drivers.
SENSE1⁺, SENSE2⁺ (Pins 21, 11/Pins 24, 14): Positive
Inputs to Differential Current Comparators. Normally con-
nected to the sources of the external P-channel MOSFETs.
SW1 (SENSE1^–), SW2 (SENSE2^–) (Pins 22, 10/Pins 1,
13): Switch Node Connections to Inductors. Also the
negative inputs to differential peak current comparators.
Normally connected to the drains of the external P-Chan-
nel MOSFETs and the inductor when not using a sense
resistor. When a sense resistor is used, it will be con-
nected between SW and SENSE⁺.
IPRG1, IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to
Select Maximum Peak Sense Voltage Threshold. These
pins select the maximum allowed voltage drop between
the SENSE⁺ and SW pins (i.e., the maximum allowed drop
across the external P-channel MOSFET) for each channel.
Tie high, low or float to select 204mV, 85mV or 125mV,
respectively.
V_FB1, V_FB2 (Pins 24, 7/Pins 3, 10): Each receives the
remotely sensed feedback voltage for its controller from
an external resistive divider across the output.
Exposed Pad (Pin 25/NA): Exposed Pad is PGND and
must be soldered to PCB.
3737f
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