LTC3737 Datasheet, PDF (20/24 Pages) Linear Technology – Dual 2-Phase, No RSENSE DC/DC Controller with Output Tracking

LTC3737
APPLICATIO S I FOR ATIO
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C_LOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Design Example
As a design example, assume V_IN will be operating from a
maximum of 4.2V down to a minimum of 2.7V (powered
by a single lithium-ion battery). Load current requirement
is a maximum of 2.5A, but most of the time it will be in a
standby mode requiring only 2mA. Efficiency at both low
and high load currents is important. Burst Mode operation
at light loads is desired. Output voltage is 2.5V. The IPRG
pin will be tied to V_IN, so the maximum current sense
threshold ∆V_SENSE(MAX) is approximately 204mV.
Maximum Duty Cycle = ^{VOUT + VD} = 93%
V_IN(MIN) + V_D
From Figure 2, SF = 57%.
R_DS(ON)(MAX)
=
5
6
•
0.9
•
SF
•
∆V_SENSE(MAX)
I_OUT(MAX) • ρ_T
= 0.027Ω
A 0.025Ω Si3473DV P-channel MOSFET is close to this
value.
The PLLLPF pin will be left floating, so the LTC3737 will
operate at its default frequency of 550kHz. For continuous
Burst Mode operation, the required minimum inductor
value is:
L_MIN
=
4.2V – 2.5V
550kHz^{} _{00..002551Ω}^{V }

2.5V
4.2V
+
+
0.3V
0.3V

=
1.40µH
PC Board Layout Checklist
When laying out the printed circuit board, use the follow-
ing checklist to ensure proper operation of the LTC3737.
• The power loop (input capacitor, MOSFET, inductor,
output diode, output capacitor) of each channel should
be as small as possible and isolated as much as
possible from the other channel’s power loop. It is
better to have two separate, smaller valued input
capacitors (e.g., two 10µF—one for each channel)
than it is to have a single larger valued capacitor (e.g.,
one 22µF) that the channels share with a common
connection.
• The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor
dividers, I_TH compensation networks and the SGND
pin.
The power grounds consist of the (–) terminal of the
input and output capacitors, the anode of the Schottky
diodes and the PGND pins. Each channel should have
its own power ground for its power loop as described
above. The power grounds for the two channels should
connect together at a common point. It is most impor-
tant to keep the ground paths with high switching
currents away from each other.
• Put the feedback resistors close to the V_FB pins. The I_TH
compensation components should also be very close to
the LTC3737.
• The current sense traces (SENSE⁺ and SENSE^–/SW)
should be Kelvin connections right at the P-channel
MOSFET source and drain.
• Keep the switch nodes (SW1, SW2) and the gate driver
nodes (PGATE1, PGATE2) away from the small-signal
components, especially the opposite channel’s feed-
back resistors, I_TH compensation components and the
current sense pins (SENSE⁺ and SENSE^–/SW).
3737f
20