LTC3737 Datasheet, PDF (18/24 Pages) Linear Technology – Dual 2-Phase, No RSENSE DC/DC Controller with Output Tracking

LTC3737
APPLICATIO S I FOR ATIO
If the external clock frequency is greater than the internal
oscillator’s frequency, f_OSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f_OSC, current is sunk continuously, pulling down the
PLLLPF pin. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage on the PLLLPF pin is adjusted until
the phase and frequency of the external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the filter capacitor C_LP holds
the voltage.
The loop filter components, C_LP and R_LP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C_LP and R_LP determine how fast the loop
acquires lock. Typically R_LP = 10k and C_LP is 2200pF to
0.01µF.
Typically, the external clock (on the SYNC/MODE pin)
input high level is 1.6V, while the input low level is 1.2V.
These levels are guaranteed to be TTL/CMOS compatible:
0.8V is guaranteed low, while 2.0V is guaranteed high.
Table 1 summarizes the different states in which the
PLLLPF pin can be used.
Table 1
PLLLPF PIN
0V
Floating
V_IN
RC Loop Filter
SYNC/MODE PIN
DC Voltage
DC Voltage
DC Voltage
Clock Signal
FREQUENCY
300kHz
550kHz
750kHz
Phase-Locked to External Clock
Fault Condition: Short Circuit and Current Limit
To prevent excessive heating of the catch diode, foldback
current limiting can be added to reduce the current in
proportion to the severity of the fault.
Foldback current limiting is implemented by adding di-
odes D_FB1 and D_FB2 between the output and the I_TH pin as
shown in Figure 11. In a hard short (V_OUT = 0V), the current
will be reduced to approximately 50% of the maximum
output current.
1/2 LTC3737
I_TH
V_FB
R2 ₊
R1
V_OUT
D_FB1
D_FB2
3737 F11
Figure 11. Foldback Current Limiting
Low Supply Operation
Although the LTC3737 can function down to below 2.4V,
the maximum allowable output current is reduced as V_IN
decreases below 3V. Figure 12 shows the amount of
change as the supply is reduced down to 2.4V. Also shown
is the effect on V_REF.
105
V_REF
100
95
MAXIMUM
SENSE VOLTAGE
90
85
80
75
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
3737 F12
Figure 12. Line Regulation of V_REF and Maximum Sense Voltage
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest amount of time
that the LTC3737 is capable of turning the top P-channel
MOSFET on and then off. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. The minimum on-time for the LTC3737 is
typically about 250ns. Low duty cycle and high frequency
applications may approach the minimum on-time limit
and care should be taken to ensure that:
( ) ^tON(MIN)
<
V_OUT + V_D
f_OSC • V_IN + V_D
3737f
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