LTC3548EDD Datasheet, PDF (6/16 Pages) Linear Technology – Dual Synchronous, 400mA/800mA, 2.25MHz

LTC3548
BLOCK DIAGRAM
MODE/SYNC 6
REGULATOR 1
V_FB1 1
0.6V
+
I_TH
EA
–
0.55V
–
UV
UVDET
+
+
OV
OVDET
0.65V
–
SHUTDOWN
SLOPE
COMP
0.35V
–
EN
BURST
+
SLEEP
BURST
CLAMP
–+
I_COMP
S
Q
RS
LATCH
R
Q
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
ANTI
SHOOT-
THRU
I_RCMP
RUN1 2
0.6V REF
OSC
RUN2 9
OSC
V_FB2 10
REGULATOR 2 (IDENTICAL TO REGULATOR 1)
PGOOD1
POR
COUNTER
PGOOD2
V_IN
5Ω
4 SW1
11 GND
V_IN
3 V_IN
8 POR
5 GND
7 SW2
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OPERATION
The LTC3548 uses a constant-frequency, current mode
architecture. The operating frequency is set at 2.25MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit a
variety of applications, the selectable Mode pin allows the
user to choose between low noise and high efficiency.
The output voltage is set by an external divider returned
to the V_FB pins. An error amplifier compares the divided
output voltage with a reference voltage of 0.6V and adjusts
the peak inductor current accordingly. An undervoltage
comparator will pull the POR output low if the output
voltage is not above –8.5% of the reference voltage. The
POR output will go high after 262,144 clock cycles (about
117ms) of achieving regulation.
6
Main Control Loop
During normal operation, the top power switch (P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the V_FB voltage is below the the reference voltage.
The current into the inductor and the load increases until
the current limit is reached. The switch turns off and
energy stored in the inductor flows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.
The peak inductor current is controlled by the internally
compensated I_TH voltage, which is the output of the
error amplifier.This amplifier compares the V_FB pin to
the 0.6V reference. When the load current increases,
the V_FB voltage decreases slightly below the reference.
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