LTC3548EDD Datasheet, PDF (14/16 Pages) Linear Technology – Dual Synchronous, 400mA/800mA, 2.25MHz

LTC3548
TYPICAL APPLICATIONS
1mm Profile Core and I/O Supplies
V_IN = 3.6V
TO 5.5V
C1*
10μF
V_OUT2 = 3.3V
AT 400mA
L2
4.7μH
C5, 68pF
RUN2 V_IN RUN1
MODE/SYNC
POR
LTC3548
SW2
SW1
R5
100k
POWER-ON
RESET
L1
2.2μH
C4, 33pF
V_OUT1 = 1.8V
AT 800mA
C3
4.7μF
V_FB2
V_FB1
R4
887k ^R3
GND
R2
R1 _604k
196k
301k
C1, C2: MURATA GRM219R60J106KE19
C3: MURATA GRM219R60J475KE19
L1: COILTRONICS LPO3310-222MX
L2: COILTRONICS LPO3310-472MX
*IF C1 IS GREATER THAN 3" FROM POWER SOURCE,
ADDITIONAL CAPACITANCE MAY BE REQUIRED.
C2
10μF
3548 TA07
Efficiency vs Load Current
100
95
3.3V
90
85
1.8V
80
75
70
65
V_IN = 5V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
60
1
10
100
LOAD CURRENT (mA)
1000
3548 TA08
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev B)
0.70 p0.05
R = 0.125
TYP
6
0.40 p 0.10
10
3.55 p0.05
1.65 p0.05
2.15 p0.05 (2 SIDES)
PACKAGE
OUTLINE
PIN 1
TOP MARK
(SEE NOTE 6)
0.25 p 0.05
0.50
BSC
2.38 p0.05
(2 SIDES)
0.200 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION
OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT
STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
3.00 p0.10 1.65 p 0.10
(4 SIDES) (2 SIDES)
0.75 p0.05
0.00 – 0.05
(DD) DFN REV B 0309
5
1
0.25 p 0.05
0.50 BSC
2.38 p0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3548fc
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