LTC3548EDD Datasheet, PDF (11/16 Pages) Linear Technology – Dual Synchronous, 400mA/800mA, 2.25MHz

LTC3548
APPLICATIONS INFORMATION
the losses in LTC3548 circuits: 1) V_IN quiescent current,
2) switching losses, 3) I²R losses, 4) other losses.
1. The V_IN current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET
driver and control currents. V_IN current results in a
small (<0.1%) loss that increases with V_IN, even at
no load.
2. The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from V_IN to ground. The resulting dQ/dt is a current
out of V_IN that is typically much larger than the DC bias
current. In continuous mode, I_GATECHG = f_O(Q_T + Q_B),
where Q_T and Q_B are the gate charges of the internal
top and bottom MOSFET switches. The gate charge
losses are proportional to V_IN and thus their effects will
be more pronounced at higher supply voltages.
3. I²R losses are calculated from the DC resistances of
the internal switches, R_SW, and external inductor,
R_L. In continuous mode, the average output current
flows through inductor L, but is “chopped” between
the internal top and bottom switches. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R_DS(ON) and the duty cycle
(D) as follows:
R_SW = (R_DS(ON)TOP)(D) + (R_DS(ON)BOT)(1 – D)
The R_DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. Thus, to obtain I²R losses:
I²R losses = (I_OUT)²(R_SW + R_L)
4. Other hidden losses such as copper trace and inter-
nal battery resistances can account for additional ef-
ficiency degradations in portable systems. It is very
important to include these system level losses in the
design of a system. The internal battery and fuse re-
sistance losses can be minimized by making sure that
C_IN has adequate charge storage and very low ESR at
the switching frequency. Other losses including diode
conduction losses during dead-time and inductor
core losses generally account for less than 2% total
additional loss.
Thermal Considerations
In a majority of applications, the LTC3548 does not dis-
sipate much heat due to its high efficiency. However, in
applications where the LTC3548 is running at high ambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will turn off and the SW node will become high
impedance.
To prevent the LTC3548 from exceeding the maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T_RISE = P_D • θ_JA
where P_D is the power dissipated by the regulator and θ_JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T_J, is given by:
T_J = T_RISE + T_AMBIENT
As an example, consider the case when the LTC3548 is
in dropout on both channels at an input voltage of 2.7V
with a load current of 400mA and 800mA and an ambi-
ent temperature of 70°C. From the Typical Performance
Characteristics graph of Switch Resistance, the R_DS(ON)
resistance of the main switch is 0.425Ω. Therefore, power
dissipated by each channel is:
P_D = (I_OUT)² • R_DS(ON) = 272mW and 68mW
The MS package junction-to-ambient thermal resistance,
θ_JA, is 45°C/W. Therefore, the junction temperature of
the regulator operating in a 70°C ambient temperature is
approximately:
T_J = (0.272 + 0.068) • 45 + 70 = 85.3°C
which is below the absolute maximum junction tempera-
ture of 125°C.
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