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| LTC3548EDD Datasheet, PDF (3/16 Pages) Linear Technology – Dual Synchronous, 400mA/800mA, 2.25MHz | |||
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LTC3548
ELECTRICAL CHARACTERISTICS The â denotes the speciï¬cations which apply over the full operating
temperature range, otherwise speciï¬cations are at TA = 25°C. VIN = 3.6V, unless otherwise speciï¬ed. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
ÎVLOADREG
IS
fOSC
fSYNC
ILIM
RDS(ON)
Output Voltage Load Regulation
(Note 3)
0.5
%
Input DC Supply Current
Active Mode
Sleep Mode
Shutdown
Oscillator Frequency
Synchronization Frequency
(Note 4)
VFB1 = VFB2 = 0.5V
VFB1 = VFB2 = 0.63V, MODE/SYNC = 3.6V
RUN = 0V, VIN = 5.5V, MODE/SYNC = 0V
700
950
μA
40
60
μA
0.1
1
μA
VFB = 0.6V
l 1.8
2.25
2.7
MHz
2.25
MHz
Peak Switch Current Limit Channel 1
Peak Switch Current Limit Channel 2
Top Switch On-Resistance
Bottom Switch On-Resistance
VIN = 3V, VFB = 0.5V, Duty Cycle <35%
VIN = 3V, VFB = 0.5V, Duty Cycle <35%
(Note 6)
(Note 6)
0.95
1.2
1.6
A
0.6
0.7
0.9
A
0.35 0.45
Ω
0.30 0.45
Ω
ISW(LKG)
POR
Switch Leakage Current
Power-On Reset Threshold
Power-On Reset On-Resistance
VIN = 5V, VRUN = 0V, VFB = 0V
VFB Ramping Down, MODE/SYNC = 0V
0.01
1
μA
â 8.5
%
100
200
Ω
Power-On Reset Delay
262,144
Cycles
VRUN
IRUN
MODE
RUN Threshold
RUN Leakage Current
Mode Threshold Low
Mode Threshold High
l 0.3
1
1.5
V
l
0.01
1
μA
0
VIN â 0.5
0.5
V
VIN
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3548 is guaranteed to meet speciï¬ed performance from
0°C to 85°C. Speciï¬cations over the â 40°C to 85°C operating temperature
range are assured by design, characterization and correlation with
statistical process controls. The LTC3548I is guaranteed to meet speciï¬ed
performance over the full â40°C to 85°C temperature range.
Note 3: The LTC3548 is tested in a proprietary test mode that connects VFB
to the output of the error ampliï¬er.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: TJ is calculated from the ambient TA and power dissipation PD
according to the following formula: TJ = TA + (PD ⢠θJA).
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise speciï¬ed.
Burst Mode Operation
Pulse-Skipping Mode
Load Step
SW
5V/DIV
VOUT
20mV/DIV
IL
200mA/DIV
VIN = 3.6V
2μs/DIV
VOUT = 1.8V
ILOAD = 180mA
CHANNEL 1; CIRCUIT OF FIGURE 3
SW
5V/DIV
VOUT
10mV/DIV
IL
200mA/DIV
3548 G01
VIN = 3.6V
1μs/DIV
VOUT = 1.8V
ILOAD = 30mA
CHANNEL 1; CIRCUIT OF FIGURE 3
VOUT
200mV/DIV
IL
500mA/DIV
ILOAD
500mA/DIV
3548 G02
VIN = 3.6V
20μs/DIV
VOUT = 1.8V
ILOAD = 80mA TO 800mA
CHANNEL 1; CIRCUIT OF FIGURE 3
3548 G03
3548fc
3
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