LTC3407A-2 Datasheet, PDF (6/16 Pages) Linear Technology – Dual Synchronous 800mA,2.25MHz Step-Down DC/DC Regulator

LTC3407A-2
PI FU CTIO S
V_FB1 (Pin 1): Output Feedback. Receives the feedback
voltage from the external resistive divider across the
output. Nominal voltage for this pin is 0.6V.
RUN/SS1 (Pin 2): Regulator 1 Enable and Soft-Start Input.
Forcing this pin to V_IN enables regulator 1, while forcing it
to GND causes regulator 1 to shut down. Connect external
RC-network with desired time-constant to enable soft-
start feature. This pin must be driven; do not float.
V_IN (Pin 3): Main Power Supply. Must be closely decoupled
to GND.
SW1 (Pin 4): Regulator 1 Switch Node Connection to the
Inductor. This pin swings from V_IN to GND.
GND (Pin 5): Main Ground. Connect to the (–) terminal of
C_OUT, and (–) terminal of C_IN.
MODE/SYNC (Pin 6): Combination Mode Selection and
Oscillator Synchronization. This pin controls the operation
of the device. When tied to V_IN or GND, Burst Mode
operation or pulse skipping mode is selected, respec-
tively. Do not float this pin. The oscillation frequency can
be synchronized to an external oscillator applied to this pin
and pulse skipping mode is automatically selected.
SW2 (Pin 7): Regulator 2 Switch Node Connection to the
Inductor. This pin swings from V_IN to GND.
POR (Pin 8): Power-On Reset. This common-drain logic
output is pulled to GND when the output voltage is not
within ±8.5% of regulation and goes high after 2¹⁶ clock
cycles when both channels are within regulation.
RUN/SS2 (Pin 9): Regulator 2 Enable and Soft-Start Input.
Forcing this pin to V_IN enables regulator 2, while forcing it
to GND causes regulator 2 to shut down. Connect external
RC-Network with desired time-constant to enable soft-
start feature. This pin must be driven; do not float.
V_FB2 (Pin 10): Output Feedback. Receives the feedback
voltage from the external resistive divider across the
output. Nominal voltage for this pin is 0.6V.
Exposed Pad (GND) (Pin 11): Power Ground. Connect to
the (–) terminal of C_OUT, and (–) terminal of C_IN. Must be
soldered to electrical ground on PCB.
BLOCK DIAGRA
MODE/SYNC 6
V_FB1 1
RUN/SS1 2
RUN/SS2 9
V_FB2 10
REGULATOR 1
0.6V +
I_TH
EA
–
0.55V
–
UV
UVDET
+
+
OV
OVDET
0.65V
–
SHUTDOWN
SLOPE
COMP
–
EN
SLEEP
0.65V
+
BURST
S
Q
RS
LATCH
R
Q
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
BURST
CLAMP
–+
I_COMP
ANTI
SHOOT-
THRU
I_RCMP
0.6V REF
OSC
OSC
REGULATOR 2 (IDENTICAL TO REGULATOR 1)
PGOOD1
POR
COUNTER
PGOOD2
6
V_IN
5Ω
4 SW1
11 GND
V_IN
3 V_IN
8 POR
5 GND
3407A2 BD
7 SW2
3407a2f