LTC3407A-2 Datasheet, PDF (13/16 Pages) Linear Technology – Dual Synchronous 800mA,2.25MHz Step-Down DC/DC Regulator

LTC3407A-2
APPLICATIO S I FOR ATIO
Choosing the next highest standardized inductor value of
2.2μH, results in a maximum ripple current of:
ΔI_L
=
2.5V
2.25MHz • 2.2μH
•
⎛
⎝⎜
1−
2.5V
4.2V
⎞
⎠⎟
=
204mA
For cost reasons, a ceramic capacitor will be used. C_OUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
C_OUT
≈
2.5
800mA
2.25MHz • (5%
•
2.5V)
=
7.1μF
The closest standard value is 10μF. Since the output
impedance of a Li-Ion battery is very low, C_IN is typically
10μF.
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2μA with the 0.6V feedback voltage makes R1~300k. A
close standard 1% resistor is 280k, and R2 is then 887k.
The POR pin is a common drain output and requires a pull-
up resistor. A 100k resistor is used for adequate speed.
Figure 3 shows the complete schematic for this design
example. The specific passive components chosen allow
for a 1mm height power supply that maintains a high
efficiency across load.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3407A-2. These items are also illustrated graphically
in the layout diagram of Figure 2. Check the following in
your layout:
1. Does the capacitor C_IN connect to the power V_IN (Pin 3)
and GND (exposed pad) as closely as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
2. Are C_OUT and L1 closely connected? The (–) plate of
C_OUT returns current to GND and the (–) plate of C_IN.
3. The resistor divider formed by R1 and R2 must be
connected between the (+) plate of C_OUT and a ground
sense line terminated near GND (exposed pad). The feed-
back signals V_FB1 and V_FB2 should be routed away from
noisy components and traces, such as the SW lines (Pins
4 and 7), and their traces should be minimized.
4. Keep sensitive components away from the SW pins. The
input capacitor C_IN and the resistors R1 to R4 should be
routed away from the SW traces and the inductors.
5. A ground plane is preferred, but if not available keep the
signal and power grounds segregated with small signal
components returning to the GND pin at one point.
Addtionally the two grounds should not share the high
current paths of C_IN or C_OUT.
6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. These copper areas should be con-
nected to V_IN or GND.
V_OUT2
V_IN
C_IN
RUN/SS2 V_IN RUN/SS1
MODE/SYNC
POR
LTC3407A-2
L2
L1
SW2
SW1
C5
C4
V_OUT1
R4
C_OUT2
V_FB2
V_FB1
GND
R2
R3
R1
C_OUT1
BOLD LINES INDICATE HIGH CURRENT PATHS
3407A2 F02
Figure 2. LTC3407A-2 Layout Diagram (See Board Layout Checklist)
3407a2f
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