LTC3407A-2 Datasheet, PDF (10/16 Pages) Linear Technology – Dual Synchronous 800mA,2.25MHz Step-Down DC/DC Regulator

LTC3407A-2
APPLICATIO S I FOR ATIO
At worst, the ringing at the input can be large enough to
damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough to
support the load. The time required for the feedback loop
to respond is dependent on the compensation and the
output capacitor size. Typically, 3-4 cycles are required to
respond to a load step, but only in the first cycle does the
output drop linearly. The output droop, V_DROOP, is usually
about 3 times the linear drop of the first cycle. Thus, a good
place to start is with the output capacitor size of approxi-
mately:
C_OUT
≈
3
f_O
ΔI_OUT
• V_DROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely re-
quired to supply high frequency bypassing, since the
impedance to the supply is very low. A 10μF ceramic
capacitor is usually enough for these conditions.
Setting the Output Voltage
The LTC3407A-2 develops a 0.6V reference voltage be-
tween the feedback pin, V_FB, and ground as shown in
Figure 1. The output voltage is set by a resistive divider
according to the following formula:
V_OUT
=
0.6V
⎛
⎝⎜
1+
R2 ⎞
R1⎠⎟
Keeping the current small (<5μA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
To improve the frequency response, a feed-forward ca-
pacitor C_F may also be used. Great care should be taken to
route the V_FB line away from noise sources, such as the
inductor or the SW line.
10
Power-On Reset
The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output
voltages are within ±8.5% of regulation, a timer is started
which releases POR after 2¹⁶ clock cycles (about 29ms in
pulse skipping mode). This delay can be significantly
longer in Burst Mode operation with low load currents,
since the clock cycles only occur during a burst and there
could be milliseconds of time between bursts. This can be
bypassed by tying the POR output to the MODE/SYNC
input, to force pulse skipping mode during a reset. In
addition, if the output voltage faults during Burst Mode
sleep, POR could have a slight delay for an undervoltage
output condition and may not respond to an overvoltage
output. This can be avoided by using pulse skipping mode
instead. When either channel is shut down, the POR
output is pulled low, since one or both of the channels are
not in regulation.
Mode Selection & Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect-
ing this pin to V_IN enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higher output voltage ripple. When this pin is connected to
ground, pulse skipping operation is selected which pro-
vides the lowest output ripple, at the cost of low current
efficiency.
The LTC3407A-2 can also be synchronized to another
LTC3407A-2 by the MODE/SYNC pin. During synchroni-
zation, the mode is set to pulse skipping and the top switch
turn-on is synchronized to the rising edge of the external
clock.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to ΔI_LOAD • ESR, where ESR is the effective series
resistance of C_OUT. ΔI_LOAD also begins to charge or
discharge C_OUT generating a feedback error signal used by
the regulator to return V_OUT to its steady-state value. During
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