LTC3832-1_15 Datasheet, PDF (3/24 Pages) Linear Technology – High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation

LTC3832/LTC3832-1
ELECTRICAL CHARACTERISTICS The q denotes specifications that apply over the full operating temperature
range, otherwise specifications are at T_A = 25°C. V_CC, PV_CC1, PV_CC2 = 5V, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
I_VCC
Supply Current
I_PVCC
PV_CC Supply Current
f_OSC
V_SAWL
V_SAWH
V_COMPMAX
∆f_OSC/∆I_FREQSET
A_V
Internal Oscillator Frequency
V_COMP at Minimum Duty Cycle
V_COMP at Maximum Duty Cycle
Maximum V_COMP
Frequency Adjustment
Error Amplifier Open-Loop DC Gain
Figure 2, V_SHDN = V_CC
V_SHDN = 0V
Figure 2, V_SHDN = V_CC (Note 3)
V_SHDN = 0V
FREQSET Floating
q
0.7
1.6
mA
q
1
10
µA
q
20
30
mA
q
0.1
10
µA
q 230
300
360
kHz
1.2
V
2.2
V
V_FB = 0V, PV_CC1 = 8V
2.85
V
10
kHz/µA
Measured from FB to COMP,
q 50
65
dB
SENSE⁺ and SENSE^– Floating, (Note 4)
g_m
Error Amplifier Transconductance
Measured from FB to COMP,
q 1600 2000 2400 µmho
SENSE⁺ and SENSE^– Floating, (Note 4)
I_COMP
I_MAX
Error Amplifier Output Sink/Source Current
I_MAX Sink Current
V_IMAX = V_CC
(Note 10)
100
µA
8
12
16
µA
q4
12
20
µA
V_IH
V_IL
I_IN
I_SS
I_SSIL
R_SENSE
R_SENSEFB
t_r, t_f
t_NOV
DC_MAX
I_MAX Sink Current Tempco
SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current
Soft-Start Source Current
Maximum Soft-Start Sink Current
In Current Limit
SENSE Input Resistance
SENSE to FB Resistance
Driver Rise/Fall Time
Driver Nonoverlap Time
Maximum G1 Duty Cycle
V_IMAX = V_CC (Note 6)
V_SHDN = V_CC
V_SS = 0V, V_IMAX = 0V, V_IFB = V_CC
V_IMAX = V_CC, V_IFB = 0V,
V_SS = V_CC (Note 8), PV_CC1 = 8V
q 2.4
q
q
q –8
Figure 2, PV_CC1 = PV_CC2 = 5V (Note 5) q
Figure 2, PV_CC1 = PV_CC2 = 5V (Note 5) q 25
Figure 2, V_FB = 0V (Note 5), PV_CC1 = 8V q 91
3300
ppm/°C
V
0.8
V
0.1
1
µA
–12 –18
µA
1.6
mA
23.7
kΩ
18
kΩ
80
250
ns
120 250
ns
95
%
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 3: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC3832 operating frequency, operating voltage and the external FETs
used.
Note 4: The open-loop DC gain and transconductance from the SENSE⁺
and SENSE^– pins to COMP pin will be (A_V)(0.6/2.5) and (g_m)(0.6/2.5)
respectively.
Note 5: Rise and fall times are measured using 10% and 90% levels. Duty
cycle and nonoverlap times are measured using 50% levels.
Note 6: Guaranteed by design, not subject to test.
Note 7: PV_CC1 must be higher than V_CC by at least 2.5V for G1 to operate
at 95% maximum duty cycle and for the current limit protection circuit to
be active.
Note 8: The current limiting amplifier can sink but cannot source current.
Under normal (not current limited) operation, the output current will be
zero.
Note 9: The LTC3832E/LTC3832-1E are guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 10: The minimum and maximum limits for I_MAX over temperature
includes the intentional temperature coefficient of 3300ppm/°C. This
induced temperature coefficient counteracts the typical temperature
coefficient of the external power MOSFET on-resistance. This results in a
relatively flat current limit over temperature for the application.
sn3832 3832fs
3