LTC3832-1_15 Datasheet, PDF (18/24 Pages) Linear Technology – High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation

LTC3832/LTC3832-1
APPLICATIO S I FOR ATIO
1. In general, layout should begin with the location of the
power devices. Be sure to orient the power circuitry so that
a clean power flow path is achieved. Conductor widths
should be maximized and lengths minimized. After you are
satisfied with the power path, the control circuitry should
be laid out. It is much easier to find routes for the relatively
small traces in the control circuits than it is to find
circuitous routes for high current paths.
2. The GND and PGND pins should be shorted directly at
the LTC3832. This helps to minimize internal ground dis-
turbances in the LTC3832 and prevent differences in ground
potential from disrupting internal circuit operation. This
connection should then tie into the ground plane at a single
point, preferably at a fairly quiet point in the circuit such as
close to the output capacitors. This is not always practical,
however, due to physical constraints. Another reasonably
good point to make this connection is between the output
capacitors and the source connection of the bottom
MOSFET Q2. Do not tie this single point ground in the trace
run between the Q2 source and the input capacitor ground,
as this area of the ground plane will be very noisy.
3. The small-signal resistors and capacitors for frequency
compensation and soft-start should be located very close
to their respective pins and the ground ends connected to
the signal ground pin through a separate trace. Do not
connect these parts to the ground plane!
4. The V_CC, PV_CC1 and PV_CC2 decoupling capacitors should
be as close to the LTC3832 as possible. The 4.7µF and 1µF
bypass capacitors shown at V_CC, PV_CC1 and PV_CC2 will help
provide optimum regulation performance.
5. The (+) plate of C_IN should be connected as close as
possible to the drain of the upper MOSFET, Q1. An additional
1µF ceramic capacitor between V_IN and power ground is
recommended.
6. The SENSE and V_FB pins are very sensitive to pickup from
the switching node. Care should be taken to isolate SENSE
and V_FB from possible capacitive coupling to the inductor
switching signal. Connecting the SENSE⁺ and SENSE^– close
to the load can significantly improve load regulation.
7. Kelvin sense I_MAX and I_FB at Q1’s drain and source pins.
PV_CC
100Ω
+
4.7µF
V_CC
PV_CC2
1µF
PV_CC1
1µF
PGND
0.1µF
G1
GND
LTC3832
I_MAX
1k
NC FREQSET
I_FB
SHDN SENSE⁺
COMP
G2
C1
R_C
SS
FB
NC
SENSE^–
GND PGND
C_C
C_SS
GND
V_IN
+
C_IN
Q1A
Q1B
Q2
PGND
L_O
V_OUT
+
C_OUT
3832 F11
Figure 11. Typical Schematic Showing Layout Considerations
18
sn3832 3832fs