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LTC3892-1_15 Datasheet, PDF (28/36 Pages) Linear Technology – 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller
◁
LTC3892/LTC3892-1
Applications Information
Design Example
As a design example for one channel, assume VIN = 12V
(nominal), VIN = 22V (maximum), VOUT = 3.3V, IMAX =
5A, VSENSE(MAX) = 75mV and f = 350kHz. The inductance
value is chosen first based on a 30% ripple current as-
sumption. The highest value of ripple current occurs at
the maximum input voltage. Tie the FREQ pin to GND,
generating 350kHz operation. The minimum inductance
for 30% ripple current is:
∆IL
=
VOUT
(f)(L)


1−
VOUT
VIN(NOM)


A 4.7μH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time
of 80ns is not violated. The minimum on-time occurs at
maximum VIN:
tON(MIN)
=
VOUT
VIN(MAX)
(
f)
=
3.3V
22V (350kHz )
=
429ns
The equivalent RSENSE resistor value can be calculated by
using the minimum value for the maximum current sense
threshold (66mV):
RSENSE
≤
66mV
5.73A
≈
0.01Ω
Choosing 1% resistors: RA = 25k and RB = 78.7k yields
an output voltage of 3.32V.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF.
At maximum input voltage with T(estimated) = 50°C:
PMAIN
=
3.3V
22V
(5A)2
1+
(0.005)(50°C
−
25°C)
(0.035Ω)
+
(22V)2
5A
2
(2.5Ω)(215pF
)
•


5V
1
− 2.3V
+
1
2.3V


(350kHz)
=
331mW
A short-circuit to ground will result in a folded back cur-
rent of:
ISC
=
34mV
0.01Ω
−
1
2


80ns(22V
4.7µH
)


=
3.21A
with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
PSYNC = (3.21A)2 (1.125) (0.022Ω) = 255mW
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VO(RIPPLE) = RESR (∆IL) = 0.02Ω (1.45A) = 29mVP-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. Figure 10 illustrates the current waveforms present in
the various branches of the 2-phase synchronous buck
regulators operating in the continuous mode. Check the
following in your layout:
1. Are the top N-channel MOSFETs MTOP1 and MTOP2
located within 1cm of each other with a common drain
connection at CIN? Do not attempt to split the input
decoupling for the two channels as it can cause a large
resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CDRVCC must return to the combined COUT (–) termi-
nals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
28
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