LTC3892-1_15 Datasheet, PDF (15/36 Pages) Linear Technology – 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller

LTC3892/LTC3892-1
Operation (Refer to the Functional Diagrams)
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to GND, tied to
INTV_CC or programmed through an external resistor. Tying
FREQ to GND selects 350kHz while tying FREQ to INTV_CC
selects 535kHz. Placing a resistor between FREQ and GND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 9.
A phase-locked loop (PLL) is available on the LTC3892/
LTC3892-1 to synchronize the internal oscillator to an
external clock source that is connected to the PLLIN/MODE
pin. The LTC3892/LTC3892-1’s phase detector adjusts the
voltage (through an internal lowpass filter) of the VCO input
to align the turn-on of controller 1’s external top MOSFET
to the rising edge of the synchronizing signal. Thus, the
turn-on of controller 2’s external top MOSFET is 180° out
of phase to the rising edge of the external clock source.
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the LTC3892/LTC3892-1’s
phase-locked loop is from approximately 55kHz to 1MHz,
with a guarantee to be between 75kHz and 850kHz. In
other words, the LTC3892/LTC3892-1’s PLL is guaranteed
to lock to an external clock source whose frequency is
between 75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.1V (falling). It is recommended
that the external clock source swing from ground (0V) to
at least 2.5V.
Output Overvoltage Protection
Each channel has an overvoltage comparator that guards
against transient overshoots as well as other more seri-
ous conditions that may overvoltage the output. When
the V_FB1,2 pin rises by more than 10% above its regula-
tion point of 0.800V, the top MOSFET is turned off and
the bottom MOSFET is turned on until the overvoltage
condition is cleared.
Foldback Current
When the output voltage falls to less than 70% of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
interval (as long as the V_FB1,2 voltage is keeping up with
the TRACK/SS1,2 voltage).
For more information www.linear.com/LTC3892
38921f
15