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LTC3892-1_15 Datasheet, PDF (25/36 Pages) Linear Technology – 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller
LTC3892/LTC3892-1
Applications Information
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on chip
(such as DRVCC short to ground), the overtemperature
shutdown circuitry will shut down the LTC3892/LTC3892-1.
When the junction temperature exceeds approximately
175°C, the overtemperature circuitry disables the DRVCC
LDO, causing the DRVCC supply to collapse and effectively
shutting down the entire LTC3892/LTC3892-1 chip. Once
the junction temperature drops back to the approximately
155°C, the DRVCC LDO turns back on. Long-term over-
stress (TJ > 125°C) should be avoided as it can degrade
the performance or shorten the life of the part.
Phase-Locked Loop and Frequency Synchronization
The LTC3892/LTC3892-1 has an internal phase-locked
loop (PLL) comprised of a phase frequency detector, a
lowpass filter, and a voltage-controlled oscillator (VCO).
This allows the turn-on of the top MOSFET of controller 1
to be locked to the rising edge of an external clock signal
applied to the PLLIN/MODE pin. The turn-on of controller
2’s top MOSFET is thus 180° out of phase with the external
clock. The phase detector is an edge sensitive digital type
that provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced continu-
ously from the phase detector output, pulling up the VCO
input. When the external clock frequency is less than fOSC,
current is sunk continuously, pulling down the VCO input.
75kHz and 850kHz. Typically, the external clock (on the
PLLIN/MODE pin) input high threshold is 1.6V, while the
input low threshold is 1.1V. The LTC3892/LTC3892-1 is
guaranteed to synchronize to an external clock that swings
up to at least 2.5V and down to 0.5V or less.
Rapid phase locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock and
synchronization. Although it is not required that the free-
running frequency be near the external clock frequency,
doing so will prevent the operating frequency from passing
through a large range of frequencies as the PLL locks.
Table 3 summarizes the different states in which the FREQ
pin can be used. When synchronized to an external clock,
the LTC3892/LTC3892-1 operates in forced continuous
mode at light loads.
Table 3
FREQ PIN
0V
INTVCC
Resistor to GND
Any of the Above
PLLIN/MODE PIN
DC Voltage
DC Voltage
DC Voltage
External Clock
75kHz to 850kHz
FREQUENCY
350kHz
535kHz
50kHz to 900kHz
Phase Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
1000
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
Note that the LTC3892/LTC3892-1 can only be synchro-
nized to an external clock whose frequency is within range
of the LTC3892/LTC3892-1’s internal VCO, which is nomi-
nally 55kHz to 1MHz. This is guaranteed to be between
900
800
700
600
500
400
300
200
100
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
38921 F10
Figure 9. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
38921f
For more information www.linear.com/LTC3892
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