LTC3868-1 Datasheet, PDF (28/38 Pages) Linear Technology – Low IQ, Dual 2-Phase Synchronous Step-Down Controller

LTC3868-1
Applications Information
Reduce V_IN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V_IN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltavges and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between C_IN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
28
SS1
LTC3868-1
I_TH1
V_FB1
SENSE1⁺
PGOOD1
TG1
SENSE1^–
SW1
FREQ
BOOST1
BG1
f_IN
PLLIN/MODE
V_IN
RUN1
RUN2
SGND
SENSE2^–
PGND
EXTV_CC
INTV_CC
V_OUT1
SENSE2⁺
BG2
V_FB2
BOOST2
I_TH2
SW2
TG2
SS2
R_PU1
V_PULL-UP
(<6V)
PGOOD1
L1
R_SENSE
C_B1
M1
M2
D1
C_VIN
R_IN
1µF
CERAMIC
C_OUT1
C_INTVCC
C_B2
V_IN
C_IN
1µF
CERAMIC
M3
M4
L2
C_OUT2
D2
R_SENSE
V_OUT1
GND
V_OUT2
Figure 10. Recommended Printed Circuit Layout Diagram
38681 F10
38681fb